Transmit Path Latency - 3.5 English

Quad Serial Gigabit Media Independent LogiCORE Product Guide (PG029)

Document ID
PG029
Release Date
2023-11-02
Version
3.5 English

As measured from a data octet input into gmii_txd[7:0] of the transmitter side GMII of SGMII on port 0 (until that data appears on txdata[7:0] on the serial transceiver interface), the latency through the core in the transmit direction is five clock periods of userclk2 .