This device-specific transceiver wrapper is instantiated from the block-level HDL file of the example design and is described in the following files:
VHDL
/synth/transceiver/<component_name>_transceiver.vhd
Verilog
/synth/transceiver/<component_name>_transceiver.v
This file instances output source files from the transceiver wizard (used with QSGMII attributes).