Transceiver Wrapper - 3.5 English - PG029

Quad Serial Gigabit Media Independent LogiCORE Product Guide (PG029)

Document ID
PG029
Release Date
2023-11-02
Version
3.5 English

This device-specific transceiver wrapper is instantiated from the block-level HDL file of the example design and is described in the following files:

VHDL

/synth/transceiver/<component_name>_transceiver.vhd

Verilog

/synth/transceiver/<component_name>_transceiver.v

This file instances output source files from the transceiver wizard (used with QSGMII attributes).