The example is split between two discrete hierarchical layers, as illustrated in the following figure. The block level is designed so that it can be instantiated directly into customer designs and provides the following functionality:
- Instantiates the core from HDL.
- Connects the client interface through the QSGMII adaptation module. See Using the Client Side GMII/MII Datapath.
- Connects the physical-side interface of the core to Versal Adaptive SoC families, UltraScale+ families, UltraScale architecture, Zynq 7000 SoC, Virtex 7, Kintex 7, or Artix 7 device transceiver.
The logic implemented in the block level for the physical-side interface of the core is illustrated in all the figures and described in further detail for the remainder of this chapter.
Virtex 7 Devices
The core is designed to integrate with the 7 series FPGA transceiver. The following figure illustrates the connections and logic required between the core and the transceiver; the signal names and logic in the figure precisely match those delivered with the example design when a 7 series FPGA transceiver is used.
The 125 MHz differential reference clock is
routed directly to the 7 series
FPGA transceiver. The transceiver is configured to output a version of this clock (125 MHz)
on the txoutclk port; this is then placed onto global clock
routing and is input back into the transceiver on the user interface clock ports txusrclk
and txusrclk2. This clock is also used to source for all
core logic.
The transceiver is configured to output a
recovered clock (125 MHz) on the rxoutclk port; this is placed onto regional routing through
BUFMR and BUFR. This clock is then used to source the receive logic from the transceiver
receive side output to the rxelastic buffer in the core. The clocking logic is included in a
separate module <component_name>_clocking which is
instantiated in the <component_name>_support
module.
The two wrapper files immediately around the
transceiver pair, gtwizard and gtwizard_gt() are generated from the 7 series FPGA transceiver wizard. These files apply all the QSGMII
attributes. Consequently, these files can be regenerated by invoking the 7 series FPGAs transceivers wizard in the Vivado Design Suite and selecting the QSGMII Protocol template on
the Line Rate, RefClk Selection tab. For more information, see the
7
Series FPGAs GTX/GTH Transceivers User Guide (UG476).
<component_name>
module level.Zynq 7000 SoC/Kintex 7 Devices
The core is designed to integrate with the 7 series FPGA transceiver. The following figure illustrates the connections and logic required between the core and the transceiver; the signal names and logic in the figure precisely match those delivered with the example design when a 7 series FPGA transceiver is used.
The 125 MHz differential reference clock is
routed directly to the 7 series
transceiver. The transceiver is configured to output a version of this clock (125 MHz) on
the txoutclk port; this is then placed onto global clock
routing and is input back into the GTXE2 transceiver on the user interface clock ports
txusrclk and txusrclk2.
This clock is also used to source for all core logic.
The transceiver is configured to output a
recovered clock (125 MHz) on the rxoutclk port; this is
placed onto global routing through BUFG. This clock is then used to source the receive logic
from Transceiver receive side output to the rxelastic buffer in the core. The clocking logic
is included in a separate module, <component_name>_clocking, which is instantiated in the <component_name>_clocking module.
The two wrapper files immediately around the GTP transceiver pair, gtwizard and gtwizard_gt (the following figure), are generated from the 7 series FPGA transceiver wizard. These files apply all the QSGMII attributes. Consequently, these files can be regenerated by invoking the 7 series FPGAs transceivers wizard in the Vivado Design Suite and selecting the QSGMII Protocol template on the Line Rate, RefClk Selection tab. For more information, see the 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476).
Artix 7 Devices
The QSGMII core is designed to integrate with the 7 series FPGA transceiver. The following diagram illustrates the connections and logic required between the core and the transceiver; the signal names and logic in the figure precisely match those delivered with the example design when a 7 series FPGA transceiver is used.
The 125 MHz differential reference clock is routed directly to the 7 series transceiver. The transceiver is configured to output a version of this clock (125 MHz) on the txoutclk port; this is then placed onto global clock routing and passed to a MMCM which generates two clocks; one 125 MHz (userclk2) and other 250 MHz (userclk). The userclk and userclk2 signals are input back into the GTPE2 transceiver on the user interface clock ports txusrclk and txusrclk2 . The userclk2 clock is also used to source for all core logic.
The transceiver is configured to output a
recovered clock (250 MHz) on the rxoutclk port. This clock
is divided down to 125 MHz using BUFR and is then used to source the receive logic from
Transceiver receive side rxelastic buffer read in the core and rxusrclk2 port of
transceiver. The 250 MHz rxoutclk is placed on regional clock routing using BUFR and is
routed back to rxuserclk port of transceiver. The clocking logic is included in separate
module, <component_name>_clocking , which is instantiated in the
<component_name>_support module. In the following figure, clocking resources BUFMR and
BUFR are used on rxoutclk. In certain devices BUFMRs are not available. In this case, other
clocking schemes need to be used with the core generated with the Include Shared
Logic in Example Design option.
The two wrapper files immediately around the GTP transceiver pair, gtwizard and gtwizard_gt (see following figure), are generated from the 7 series FPGA transceiver wizard. These files apply all the QSGMII attributes. Consequently, these files can be regenerated by invoking the 7 series FPGAs transceivers wizard in the Vivado Design Suite and selecting the QSGMII Protocol template on the Line Rate, RefClk Selection tab. For more information, see the 7 Series FPGAs GTP Transceivers User Guide (UG482).
UltraScale and UltraScale+ Devices
The core is designed to integrate with the UltraScale device transceiver. The following figure illustrates the connections and logic required between the core and the transceiver; the signal names and logic in the figure precisely match those delivered with the core hdl when an UltraScale and UltraScale+ device transceivers are used.
The 125 MHz differential reference clock is routed directly
to the transceiver. The transceiver is configured to output a version of this clock (125
MHz) on the txoutclk port; this is then placed onto global clock routing
and is input back into the transceiver on the user interface clock ports
txusrclk and txusrclk2. This clock is also used to
source all core logic.
The transceiver is configured to output a recovered clock
(125 MHz) on the rxoutclk port; this is placed onto global routing through
BUFG_GT. This clock is then used to source the receive logic from transceiver receive side
output to the rxelastic buffer in the core. The clocking logic is included
in a separate module, <component_name>_clocking , which is instantiated in the
<component_name>_support module.
The transceiver subcore is auto generated and instantiated when the QSGMII core is generated.