The example is split between two discrete hierarchical layers, as illustrated in This Figure . The block level is designed so that it can be instantiated directly into customer designs and provides the following functionality:
• Instantiates the core from HDL.
• Connects the client interface through the QSGMII adaptation module. See Using the Client Side GMII/MII Datapath .
• Connects the physical-side interface of the core to Versal ™ Adaptive SoC families, UltraScale+ families, UltraScale architecture, Zynq 7000 SoC, Virtex 7, Kintex 7, or Artix 7 device transceiver.
The logic implemented in the block level for the physical-side interface of the core is illustrated in all the figures and described in further detail for the remainder of this chapter.