Transceiver Files for Zynq 7000 SoC, Virtex 7, Kintex 7, or Artix 7 Devices - 4.0 English - PG029

Transceiver Wrapper

This device-specific transceiver wrapper is instantiated from the block-level HDL file of the example design and is described in the following files:

VHDL

/synth/transceiver/<component_name>_transceiver.vhd

Verilog

/synth/transceiver/<component_name>_transceiver.v

This file instances output source files from the transceiver wizard (used with QSGMII attributes).

Zynq 7000 SoC, Virtex 7, Kintex 7, and Artix 7 Device Transceiver Wizard Files

The transceiver wrapper file directly instantiates device-specific transceiver wrapper files created from the transceiver wizard. These files tie off (or leave unconnected) unused I/O for the transceiver, and apply the QSGMII attributes. The files can be edited/tailored by rerunning the wizard and swapping these files. The files delivered might include some or all of the following:

VHDL

/synth/transceiver/<component_name>_gtwizard_init.vhd
/synth/transceiver/<component_name>_gtwizard_tx_startup_fsm.vhd
/synth/transceiver/<component_name>_gtwizard_rx_startup_fsm.vhd
/synth/transceiver/<component_name>_gtwizard_gtp_gtrxreset_seq.vhd
/synth/transceiver/<component_name>_gtwizard_gtp_rxpmarst_seq_vhd.vhd
/synth/transceiver/<component_name>_gtwizard_gtp_rxrate_seq.vhd
/synth/transceiver/<component_name>_gtwizard.vhd
/synth/transceiver/<component_name>_gtwizard_gt.vhd
/synth/transceiver/component_name>_gtwizard_multi_gt.vhd

Verilog

/synth/transceiver/<component_name>_gtwizard_init.v
/synth/transceiver/<component_name>_gtwizard_tx_startup_fsm.v
/synth/transceiver/<component_name>_gtwizard_rx_startup_fsm.v
/synth/transceiver/<component_name>_gtwizard_gtp_gtrxreset_seq.v
/synth/transceiver/<component_name>_gtwizard_gtp_rxpmarst_seq_vhd.v
/synth/transceiver/<component_name>_gtwizard_gtp_rxrate_seq.v
/synth/transceiver/<component_name>_gtwizard.v
/synth/transceiver/<component_name>_gtwizard_gt.v
/synth/transceiver/component_name>_gtwizard_multi_gt.v