Transceiver Control and Status Ports - 4.0 English

This section describes optional ports that, if enabled, allow the monitoring and control of certain important transceiver ports. When not selected, these ports are tied to their default values.

Important: The ports in the Transceiver Control and Status Interface must be driven in accordance with the appropriate GT user guide. Using the input signals listed in the following table might result in unpredictable behavior of the IP core.

Note: The Dynamic Reconfiguration Port is only available if this option is selected. Also for UltraScale+ families and UltraScale devices, the prefix of ports in the following table are changed from "gt0" to "gt" and the suffix "_in" and "_out" are dropped. The IP does not provide Transceiver Control and Status Ports for Versal adaptive SoC families.

Table 1. Transceiver Control and Status Ports
Signal	Direction	Clock Domain	Description
gt0_drp_addr_in[8:0]	Input	gt0_drpclk_in	DRP address bus `drp_en` IN DRP enable signal. 0: No read or write operation performed. 1: enables a read or write operation.
gt0_drpi_in[15:0]	Input	gt0_drpclk_in	Data bus for writing configuration data to the transceiver.
gt0_drpo_out[15:0]	Output	gt0_drpclk_in	Data bus for reading configuration data from the transceiver.
gt0_drprdy_out	Output	gt0_drpclk_in	Indicates operation is complete for write operations and data is valid for read operations.
gt0_drp_busy_out	Output	gt0_drpclk_in	Output valid only for Artix 7 family. Indicates that DRP interface is busy. This bit should be checked before any transaction is posted on DRP interface.
gt0_drpwe_in	Input	gt0_drpclk_in	DRP write enable. 0: Read operation when DRPEN is 1. 1: Write operation when DRPEN is 1.
gt0_drpclk_in	Input	N/A	DRP Clock
gt0_rxchariscomma_out[3:0]	Output	rxuserclk2	GT Status
gt0_rxcharisk_out[3:0]	Output
gt0_rxbyteisaligned_out	Output
gt0_rxbyterealign_out	Output
gt0_rxcommadet_out	Output
gt0_txdiffctrl_in[3:0]	Input	Async	GT TX Driver
gt0_txpostcursor_in[4:0]	Input	Async
gt0_txprecursor_in[4:0]	Input	Async
gt0_txpolarity_in	Input	userclk2	GT Polarity
gt0_rxpolarity_in	Input	rxuserclk2	GT Polarity
gt0_txprbssel_in[2:0]	Input	userclk2	GT PRBS
gt0_txprbsforceerr_in	Input	userclk2
gt0_rxprbscntreset_in	Input	rxuserclk2
gt0_rxprbserr_out	Output	rxuserclk2
gt0_rxprbssel_in[2:0]	Input	rxuserclk2
gt0_loopback_in[2:0]	Input	Async	GT Loopback
gt0_txresetdone_out	Output	userclk2	GT Status
gt0_rxresetdone_out	Output	rxuserclk2
gt0_rxdisperr_out[3:0]	Output	rxuserclk2
gt0_rxnotintable_out[3:0]	Output	rxuserclk2
gt0_eyescanreset_in[3:0]	Input	Async	GT Eye Scan
gt0_eyescandataerror_out	Output	Async
gt0_eyescantrigger_in	Input	rxuserclk2
gt0_rxrate_in[2:0]	Input	rxuserclk2
gt0_rxcdrhold_in	Input	Async	GT CDR
gt0_rxcdrlock_out	Output	Async	GT CDR
gt0_rxratedone_out	Output	rxuserclk2	GT Fabric Clock Output Control
gt0_rxlpmhfhold_in	Input	Async	GT GTP Low Power Mode (LPM)
gt0_rxlpmlfhold_in	Input
gt0_rxlpmhfovrden_in	Input
gt0_rxlpmreset_in	Input
gt0_rxlpmen_in	Input	Async	GT GTX/GTH RX Decision Feedback Equalizer (DFE)
gt0_rxdfelpmreset_in	Input	Async
gt0_rxdfeagcovrden_in	Input	rxuserclk2
gt0_rxmonitorout_out[6:0]	Output	Async
gt0_rxmonitorsel_in[1:0]	Input
gt0_dmonitorout_out[16:0]	Output
gt0_gttxreset_in	Input	Async	TX Reset (`gt0_gttxreset_in` present in only non-UltraScale devices).
gt0_txpcsreset_in	Input
gt0_txpmareset_in	Input
gt0_gtrxreset_in	Input	Async	RX Reset (`gt0_gtrxreset_in` present in only non-UltraScale devices. `gt0_rxpmaresetdone_out` is tied to 1 for devices supporting GTX transceivers).
gt0_rxpcsreset_in	Input
gt0_rxpmareset_in	Input
gt0_rxpmaresetdone_out	Output
gt0_cplllock_out	Output	Async	Channel PLL locked. Present only in non GTP transceiver devices.
gt0_txbufstatus_out[1:0]	Output	userclk2	Transmitter buffer status.
gt0_txinhibit_in	Input	userclk2	Blocks transmission.
gt_pcsrsvdin[15:0]	Input	Async	DRP Reset. Available only for UltraScale+ families and UltraScale devices.
gt_powergood_out	Output	Async	Indicates power is good. Available only for UltraScale and UltraScale+ devices.

Transceiver Control and Status Ports - 4.0 English - PG029

Quad Serial Gigabit Media Independent LogiCORE IP Product Guide (PG029)