The top-level example design for the QSGMII core is described in the following files:
VHDL
/example_design/<component_name>_example_design.vhd
Verilog
/example_design/<component_name>_example_design.v
The example design HDL top-level contains the following:
• An instance of the QSGMII block level in case shared logic in the core is selected, otherwise support level.
• Clock management logic for the core and the device-specific transceiver, including DCM (if required) and Global Clock Buffer instances.
The example design HDL top-level connects the GMII interfaces of the block level to external IOBs. This allows the functionality of the core to be demonstrated using a simulation package, as described in this guide.