The demonstration test bench performs the following tasks:
• Input clock signals are generated.
• A reset is applied to the example design.
• Each channel of the QSGMII core is configured through the MDIO interface by injecting an MDIO frame into the example design. This disables Auto-Negotiation and takes the core out of Isolate state.
• The speed of the interface is programmed as follows:
° MAC mode
- Channel 0 – 1 Gbps
- Channel 1 – 100 Mbps
- Channel 2 – 10 Mbps
- Channel 3 – 1 Gbps
° PHY mode with GMII; all channels at 1 Gbps
° PHY mode with MII
- Channel 0 – 10 Mbps
- Channel 1 – 100 Mbps
- Channel 2 – 10 Mbps
- Channel 3 – 100 Mbps
• The following frames are injected into the transmitter by the send frame block.
° the first is a minimum length frame
° the second is a type frame
° the third is an errored frame
° the fourth is a padded frame
• The serial data received at the device-specific transceiver transmitter interface is converted to 10-bit parallel data, then 8B/10B decoded. The resultant byte is aligned to the corresponding channel based on the K28.1 character set and also the K28.1 character set is replaced with K28.5. The resulting frames are checked by in the monitor test bench against the stimulus frames injected into the transmitter to ensure data integrity.
• The same four frames are generated by the frame generator module in the receive side of the transceiver. The data from all four instances are aggregated into 32 bits, are 8B/10B encoded, converted to serial data, and injected into the device-specific transceiver receiver interface at 5 Gbps.
• Data frames received at the receiver GMII interface are checked by the Monitor against the stimulus frames injected into the device-specific transceiver receiver to ensure data integrity.