This chapter contains information about the test bench provided in the AMD Vivado ™ Design Suite.
This Figure illustrates the demonstration test bench for the QSGMII core. The demonstration test bench is a simple VHDL or Verilog program to exercise the example design and the core itself.
The top-level test bench entity instantiates the example design for the core, which is the device under test (DUT). Other modules needed to provide stimulus, clocks, resets, and test bench semaphores are also instantiated in the top-level test bench. The following files describe the top-level of the demonstration test bench.
VHDL
/simulation/demo_tb.vhd
Verilog
/simulation/demo_tb.v
Send frame test bench generates the stimulus to excite the transceiver on the DUT receive side and data input on the DUT QSGMII adapt side. Four instances of the send frame test bench are instantiated, with each instance representing one channel.
VHDL
/simulation/send_frame_tb.vhd
Verilog
/simulation/send_frame_tb.v
The Arbiter module selects one byte from each instance of the send frame test bench and passes it on to the 8B/10B encoder module.
VHDL
/simulation/arbiter_tb.vhd
Verilog
/simulation/arbiter_tb.v
The 8B/10B encoder test bench module converts 8-bit data from arbiter to 10 bits as specified by IEEE 802.3-2008 Specification [Ref 2] standard clause 36.
VHDL
/simulation/encode_8b10b_tb.vhd
Verilog
/simulation/encode_8b10b_tb.v
The 8B/10B decoder test bench module converts 10-bit data from SerDes on the transceiver transmit interface to 10 bits as specified by IEEE 802.3-2008 Specification [Ref 2] standard clause 36.
VHDL
/simulation/decode_8b10b_tb.vhd
Verilog
/simulation/decode_8b10b_tb.v
The SerDes module serializes the 10-bit data from the 8B/10B encoder and maps it to the receive interface of the DUT transceiver. This module de-serializes the serial bitstream from the transmit interface of the DUT transceiver and maps it to the 8B/10B decoder.
VHDL
/simulation/serdes_tb.vhd
Verilog
/simulation/serdes_tb.v
The K28.1 swapper module swaps K28.1 characters received on port 0 with K28.5 as specified in the QSGMII specification.
VHDL
/simulation/k28p1_swapper_tb.vhd
Verilog
/simulation/k28p1_swapper_tb.v
The Monitor test bench module monitors the output from the DUT and verifies the data with pre loaded data structures present in the module.
VHDL
/simulation/monitor_tb.vhd
Verilog
/simulation/monitor_tb.v
The programing of per channel configuration registers in the DUT is performed through MDIO configuration test bench. There are four instances of this module with each instance representing one channel.
VHDL
/simulation/mdio_cfg_tb.vhd
Verilog
/simulation/mdio_cfg_tb.v