The QSGMII core provides the functionality to implement the sublayers as specified by the Cisco QSGMII specification.
The QSGMII core interfaces to a device-specific transceiver. The transceiver provides some of the PCS functionality, such as 8B/10B encoding/decoding, Physical Medium Attachment (PMA) Serializer/Deserializer (SerDes), and clock recovery. The following diagram illustrates the remaining PCS sublayer functionality and also shows the major functional blocks of the core.
SGMII
The following figure illustrates the sub-blocks of the SGMII module.
GMII/MII Block
A client-side GMII is provided with the core, which can be used as an internal interface for connection to an embedded Media Access Controller (MAC) or other custom logic in MAC mode. In PHY mode, the GMII/MII can be routed to device Input Output Blocks (IOBs) to provide an external (off-device) GMII/MII.
AMD Virtex™ 7 devices support GMII at 3.3V or lower only in certain parts and packages. See the Virtex 7 Family home page. AMD Zynq™ 7000 SoC, AMD Kintex™ 7, and AMD Artix™ 7 devices support GMII at 3.3V or lower.
PCS Transmit Engine
The Physical Coding Sublayer (PCS) transmit engine converts the GMII data octets into a sequence of ordered sets by implementing the state diagrams of IEEE 802.3-2008 Specification (Figures 36-5 and 36-6). The transmit engine transmits only /I1/ characters instead of /I2/, as described in the QSGMII specification.
PCS Receive Engine and Synchronization
The synchronization process implements the state diagram of IEEE 802.3-2008 Specification (Figure 36-9). The PCS receive engine converts the sequence of ordered sets to GMII data octets by implementing the state diagrams of IEEE 802.3-2008 Specification (Figures 36-7a and 36-7b). This module can be programmed to optionally consider disparity. Disparity checking is disabled by default.
Optional Auto-Negotiation Block
Clause 37 in the IEEE 802.3-2008 Specification Clauses 35, 36 and 38 describes the Auto-Negotiation function that allows a device to advertise the modes of operation that it supports to a device at the remote end of a link segment (link partner), and to detect corresponding operational modes that the link partner might be advertising.
Auto-Negotiation is controlled and monitored through the PCS Management registers.
Optional PCS Management Registers
Configuration and status of the core, including access to and from the optional Auto-Negotiation function, uses the Management registers defined in clause 37 of the IEEE 802.3-2008 Specification Clauses 35, 36 and 38. These registers are accessed through the serial Management Data Input/Output Interface (MDIO), defined in clause 22 of the IEEE 802.3-2008 Specification Clauses 35, 36 and 38, as if it were an externally connected PHY.
An additional configuration vector and status signal interface is provided to configure Base Control register (Register 0) and Auto-Negotiation Ability Advertisement register (Register 4).
Aggregator
The Aggregator implements a portion of a modified transmit path diagram (Figure 1 of the QSGMII v1.2 specification). This module receives data and control from each instance of the SGMII module which is aggregated to 32-bit data and 4-bit control and transferred to Transceiver Interface block. The Aggregator also incorporates the K28.5 swapping function on port 0 that assists in port matching at the peer receiver end.
Aligner
The Aligner receives 32 bits of data from the transceiver interface. Port 0 data can be received on any lane, so a search for the K28.1 character is done on all the lanes to start lane alignment. After a match for K28.1 is found in the octet boundary in the 32-bit data, that octet boundary becomes the start of arbitration and the octet assigned to port 0. The next octet is assigned to port 1 and so on. This module also swaps any K28.1 character received on port 0 with the K28.5 character.
Transceiver Interface Block
The Transceiver Interface Block enables the core to connect to UltraScale+ families, UltraScale architecture, Zynq 7000 SoC, Virtex 7, Kintex 7, or Artix 7 device serial transceiver.
Elastic Buffer
An Elastic Buffer is instantiated on each port to perform clock correction. The clock correction involves additions and removal of /I1/ characters if disparity is ignored or /I2/ if the disparity is considered. This buffer is 128 locations deep.