The following files describe the block level for the QSGMII core. The files can be found in the /synth directory if shared logic in the core is selected or /example_design if shared logic in the example design is selected while generating the core.
VHDL
/synth/<component_name>_support.vhd or
/example_design/support/<component_name>_support.vhd
Verilog
/synth/<component_name>_support.vhd or
/example_design/support/<component_name>_support.vhd
<component_name>_support module instantiates idelayctrl , clocking, and reset modules.
VHDL
/synth/<component_name>_idelayctrl.vhd or
/example_design/support/<component_name>_idelayctrl.vhd
/synth/<component_name>_clocking.vhd or
/example_design/support/<component_name>_clocking.vhd
/synth/<component_name>_resets.vhd or
/example_design/support/<component_name>_resets.vhd
Verilog
/synth/<component_name>_idelayctrl.v or
/example_design/support/<component_name>_idelayctrl.v
/synth/<component_name>_clocking.v or
/example_design/support/<component_name>_clocking.v
/synth/<component_name>_resets.v or
/example_design/support/<component_name>_resets.v