Shared Logic Options in Vivado IDE - 3.5 English

This Figure displays the shared logic options and transceiver control and status selection in the Vivado IDE. However, Shared Logic tab is not available for Versal ™ Adaptive SoC families.

Figure 6-3: Shared Logic Options

X-Ref Target - Figure 6-3

• Shared Logic – Determines whether some shared clocking logic is included as part of the core or as part of the example design.