As part of the hierarchical changes to the core, it is now possible to have the core itself include all of the logic that can be shared between multiple cores, which was previously exposed in the example design for the core.
If you are updating a previous version to the v3.0 with Shared Logic, there is no simple upgrade path; it is recommended to consult the Shared Logic sections of this document for more guidance.
Port Changes from v3.3 to v3.4
Between QSGMII v4.3 and QSGMII v4.4, a single output port, gt_powergood_out was added. This signal indicates that CPLL calibration has been completed in the GTWIZARD. This signal should be tied to CE pin of BUFG_GT if used, otherwise, left open.