Revision History - 3.5 English

Quad Serial Gigabit Media Independent LogiCORE Product Guide (PG029)

Document ID
PG029
Release Date
2023-11-02
Version
3.5 English

The following table shows the revision history for this document.

Date

Version

Revision

11/02/2023

3.5

Editorial fixes.

02/04/2021

3.5

Added support for Versal™ Adaptive SoC

Unavailability of Shared Logic tab for Versal™ Adaptive SoC .

Removed MIDI information from configuration_vector_chx[5:0].

Editorial fixes.

12/20/2017

3.4

Added GT Data Valid signal to management registers and configuration vector interface.

06/07/2017

3.4

Added gt_powergood_out port.

Removed device resource utilization tables.

10/05/2016

3.3

Added Spartan-7 to IP Facts table.

Updated description in RX Gmii Clk Source.

Fixed 10 Mbps operation in Changing the Operational Speed section in Test Bench chapter.

04/06/2016

3.3

Added support for RX path run on rxuserclk2.

11/18/2015

3.3

Added support for UltraScale+ families.

Support for Kintex UltraScale+ GTHE4 transceivers.

09/30/2015

3.3

Updated gt0_txdiffctrl_in[3:0] clock domain to Async in Transceiver Control and Status Ports.

Support for Zynq 7000 GTHE4 transceivers.

04/01/2015

3.3

Updated Figs. 2-1 to 2-8.

Updated Table 2-15: Transceiver Control and Status Ports.

Added GT Port important note in Transceiver Control and Status Ports section.

Updated Core Customization Vivado IDE section.

Added Transceiver Clocking and Location in Table 6-1: Vivado IDE Parameter to User Parameter Relationship.

Added UNISIM important note in Simulation section.

Added Port Changes from v3.2 to v3.3 section in Migrating and Upgrading chapter.

10/01/2014

3.2

Updated to include FPGA transceivers wizard information.

06/04/2014

3.2

Update to Migrating section in Appendix B, Migrating and Updating.

User Parameters section showing relationship between Vivado IDE fields and user parameters added to Chapter 6, Design Flow Steps.

04/02/2014

3.2

Updated for the 7 series device serial transceivers (TX/RX startup FSM updates).

Changed the definition of the resetdone port to now indicate the completion of the RX and TX startup sequence.

12/18/2013

3.1

Added UltraScale™ architecture support.

Updated serial transceivers for 7 series devices (RX/TX Startup FSM updates.)

Increased the number of optional transceiver control and status ports

Updated screen captures in Chapter 6.

Changed all signal and port names in figures to all lowercase.

10/02/2013

3.0

Removed static MDIO PHY Address ports and made programmable while generation through Vivado IDE.

Removed Link Timer ports and tied to 1.64 ms for synthesis and 0.14 ms for simulation.

Updated for 7 series transceivers (Termination settings updates, attribute updates, hierarchy update).

Enhanced support for IP Integrator.

Reduced warnings in synthesis and simulation.

Updated clock synchronizers to improve Mean Time Between Failures (MTBF) for metastability.

Added support for the out-of-context flow.

Added Vivado IDE option to include or exclude shareable logic resources in the core.

Added Vivado IDE option to include or exclude configuration vector ports.

Added optional transceiver control and status ports.

03/20/2013

2.0

Revision number advanced to N.N to align with core version number.

Removed ISE-related information.

Updated resource numbers.

Updated Vivado IDEs

10/16/2012

1.4

Updated for 14.3 and 2012.3 support

Added support for AMD Zynq 7000 devices

07/25/2012

1.3

Added Vivado tools support. Added support for AMD Artix 7 devices.

04/24/2012

1.2

Added support for AMD Virtex 7 FPGA GTH Transceiver.

01/18/2012

1.0

Initial Xilinx release