Revision History - 4.0 English - PG029

Quad Serial Gigabit Media Independent LogiCORE IP Product Guide (PG029)
Document ID
PG029
Release Date
2025-12-09
Version
4.0 English

The following table shows the revision history for this document.

Section Revision Summary
12/09/2025 Version 4.0
Customizing and Generating the Core Updated screenshots.
Example Design Added two primary GT Wizard configurations for Adaptive SoC example design.
11/02/2023 Version 3.5
Multiple sections Editorial changes
02/04/2021 Version 3.5
Multiple sections
  • Added support for AMD Versal™ Adaptive SoC
  • Unavailibility for Shared Logic tab for Versal Adaptive SoC
  • Removed MIDI information from configuration_vector_chx[5:0]
  • Editorial fixes
06/07/2017 Version 3.4
Transceiver Control and Status Ports
  • Added gt_powergood_out port
  • Removed device resource utilization tables
10/05/2016 Version 3.3
IP Facts Added Spartan-7
Design Flow Steps Added description for RX GMII Clk Source
Test Bench Fixed 10 Mb/s operation
04/06/2016
Multiple sections Added support for RX path run on rxuserclk2
11/18/2015 Version 3.3
Multiple sections
  • Added support for UltraScale+ families
  • Support for Kintex UltraScale+ GTHE4 transceivers
09/30/2015 Version 3.3
Transceiver Control and Status Ports Updated gt0_txdiffctrl_in[3:0] clock domain to Async
Multiple sections Support for AMD Zynq™ 7000 GTHE4 transceivers
04/01/2015 Version 3.3
Transceiver Control and Status Ports Updated figures, ports, clocking
Simulation Added UNISIM important note
Migrating Added Port Changes from v3.2 to v3.3
10/01/2024 Version 3.2
Transceiver Logic Updated to include FPGA transceivers
06/04/2014 Version 3.2
Migrating Updated section.
04/02/2014 Version 3.2
Multiple sections
  • Updated for the 7 series device serial transceivers (TX/RX startup FSM updates)
  • Changed the definition of the resetdone port to now indicate the completion of the RX and TX startup sequence
12/18/2013 Version 3.1
Multiple sections
  • Added UltraScale architecture support
  • Updated serial transceivers for 7 series devices (RX/TX Startup FSM updates)
  • Increased the number of optional transceiver control and status ports
  • Updated screen captures
  • Changed signal and port names to lowercase
10/02/2013 Version 3.0
Multiple sections
  • Removed static MDIO PHY Address ports and made programmable while generation through Vivado IDE.
  • Removed Link Timer ports and tied to 1.64 ms for synthesis and 0.14 ms for simulation.
  • Updated for 7 series transceivers (Termination settings updates, attribute updates, hierarchy update).
  • Enhanced support for IP integrator.
  • Reduced warnings in synthesis and simulation.
  • Updated clock synchronizers to improve Mean Time Between Failures (MTBF) for metastability.
  • Added support for the out-of-context flow.
  • Added Vivado IDE option to include or exclude shareable logic resources in the core.
  • Added Vivado IDE option to include or exclude configuration vector ports.
  • Added optional transceiver control and status ports.
03/20/2013 Version 2.0
Multiple sections
  • Revision number advanced to N.N to align with core version number
  • Removed -related information
  • Updated resource numbers
  • Updated Vivado IDEs
10/16/2012 Version 1.4
Multiple sections
  • Updated for 14.3 and 2012.3 support
  • Added support for AMD Zynq 7000 devices
07/25/2012 Version 1.3
Multiple sections Added Vivado tools support. Added support for AMD Artix 7 devices
04/24/2012 Version 1.2
Multiple sections Added support for AMD Virtex 7 FPGA GTH Transceiver
01/18/2012 Version 1.0
Initial Release N/A