Register 5: SGMII Auto-Negotiation Link Partner Ability - 4.0 English - PG029

Quad Serial Gigabit Media Independent LogiCORE IP Product Guide (PG029)

Document ID
PG029
Release Date
2025-12-09
Version
4.0 English
Figure 1. MDIO Register 5: SGMII Auto-Negotiation Link Partner Ability Page-1 Sheet.1 Sheet.2 Sheet.3 Sheet.4 Sheet.5 Sheet.6 Sheet.7 Sheet.8 15 15 Sheet.9 14 14 Sheet.10 13 13 Sheet.11 12 12 Sheet.12 11 11 Sheet.13 10 10 Sheet.14 9 9 Sheet.15 Sheet.16 1 1 Sheet.17 0 0 Sheet.18 REG 5 REG 5 Sheet.19 PHY LINK STATUS PHY LINK STATUS Sheet.20 DUPLEX MODE DUPLEX MODE Sheet.21 SPEED SPEED Sheet.22 RESERVED RESERVED Sheet.23 MDIO REGISTER 5: SGMII AUTO-NEGOTIATION LINK PARTNER ABILITY MDIO REGISTER 5: SGMII AUTO-NEGOTIATION LINK PARTNER ABILITY Sheet.24 ACKNOWLEDGE ACKNOWLEDGE Sheet.25 RESERVED RESERVED Sheet.26 RESERVED RESERVED Sheet.27 X13237 X13237

The Auto-Negotiation Ability Base register (Register 5) contains information related to the status of the link between the PHY and its physical link partner across the Medium.

Table 1. SGMII Auto-Negotiation Link Partner Ability Base (Register 5)
Bits Name Description Attributes Default Value
5.15 PHY Link Status

This refers to the link status of the PHY with its link partner across the Medium.

1 = Link Up

0 = Link Down

read only 1
5.14 Acknowledge Used by Auto-Negotiation function to indicate reception of a link partner base or next page read only 0
5.13 Reserved Always returns 0, writes ignored returns 0 0
5.12 Duplex Mode

1= Full Duplex

0 = Half Duplex

read only 0
5.11:10 Speed

11 = Reserved

10 = 1 Gb/s

01 = 100 Mb/s

00 = 10 Mb/s

read only 00
5.9:1 Reserved Always return 0s returns 0s 000000000
5.0 Reserved Always returns 1 returns 1 1