Figure 1. MDIO Register 18: SGMII Generic Control
| Bits | Name | Description | Attributes | Default Value |
|---|---|---|---|---|
| 18.15:2 | Reserved | Always return 0s | returns 0s | 000000000000000 |
| 18.0 | Running Disparity Enable |
1 =Running Disparity Checking enabled 0 = Running Disparity Checking disabled |
read/ write |
0 |
| 18.1 | GT Channel Valid |
1 = Enabling contribution of status_vector[1] for data valid generation to RX FSM for the channel. 0 = Disabling contribution of status_vector[1] for data valid generation to RX FSM for the channel. This register bit is valid only for 7 series devices. |
read/write | 1 |