Register 18: SGMII Generic Control (Register 18)

Quad Serial Gigabit Media Independent LogiCORE Product Guide (PG029)

Document ID

PG029

Release Date

2023-11-02

Version

3.5 English

Figure 2-31: MDIO Register 18: SGMII Generic Control
X-Ref Target - Figure 2-31

Table 2-33: SGMII Generic Control (Register 18)
Bits	Name	Description	Attributes	Default Value
18.15:2	Reserved	Always return 0s	returns 0s	000000000000000
18.0	Running Disparity Enable	1 =Running Disparity Checking enabled 0 = Running Disparity Checking disabled	read/ write	0
18.1	GT Channel Valid	1 = Enabling contribution of status_vector[1] for data valid generation to RX FSM for the channel. 0 = Disabling contribution of status_vector[1] for data valid generation to RX FSM for the channel. Note: This register bit is valid only for 7 series devices.	read/write	1