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X-Ref Target - Figure 2-24 
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|
Bits |
Name |
Description |
Attributes |
Default Value |
|---|---|---|---|---|
|
16.15:2 |
Reserved |
Always return 0s |
returns 0s |
00000000000000 |
|
16.1 |
Interrupt Status |
1 = Interrupt is asserted 0 = Interrupt is not asserted If the interrupt is enabled, this bit is asserted on completion of an Auto-Negotiation cycle across the SGMII link; it is only cleared by writing 0 to this bit. If the Interrupt is disabled, the bit is set to 0. Note: The an_interrupt port of the core is wired to this bit. |
read/write |
0 |
|
16.0 |
Interrupt Enable |
1 = Interrupt enabled 0 = Interrupt disabled |
read/write |
1 |