QSGMII Operating in MAC Mode
This module accepts received data from the QSGMII core. This data is sampled and sent out of the GMII receiver interface for the attached client MAC. The 1 Gb/s and 100 Mb/s cases are illustrated in the following figure.
At 1 Gb/s, the data is valid on every clock cycle of the 125
MHz reference clock (clk125m). Data received from the core is clocked
straight through the Receiver Rate Adaptation module.
At 100 Mb/s, the data is repeated for a 10 clock period
duration of clk125m; at 10 Mb/s, the data is repeated for a 100 clock
period duration of clk125m. The Receiver Rate Adaptation Module samples
this data using the sgmii_clk_en clock enable.
The Receiver Rate Adaptation module also performs a second
function that accounts for the latency inferred in the following figure. The 8-bit SFD code
is detected, and if required, it is realigned across the 8-bit datapath of
gmii_rxd_out[7:0] before being presented to the attached client MAC. It
is possible that this SFD could be skewed across two separate bytes by MACs operating on a
4-bit datapath.
At all speeds, the client MAC logic should sample the GMII
receiver data synchronously to the rising edge of the 125 MHz reference clock while using
sgmii_clk_en (derived from the Clock Generation module) as a clock
enable. The frequency of the sgmii_clk_en clock enable signal ensures the
correct data rate and correct data sampling between the two devices.
QSGMII Operating in PHY Mode
This module accepts received data from the QSGMII core. This data is sampled and sent out of the GMII receiver interface for the attached external PHY. The 1 Gb/s and 100 Mb/s cases are illustrated in the following figure.
At 1 Gb/s the data is valid on every clock cycle of the 125 MHz reference clock (clk125m). Data received from the core is clocked straight through the Receiver Rate Adaptation module.
At 100 Mb/s, the data is repeated for a 10 clock period duration of clk125m; at 10 Mb/s, the data is repeated for a 100 clock period
duration of clk125m. The Receiver Rate Adaptation Module samples this data
using the sgmii_clk_en clock enable. The lower half of the
byte is sent on the LSB four bits of gmii_rxd_out[3:0]
followed by the upper nibble. This operation is done on sgmii_ddr_clk_en.