Receive Path Latency is variable because of an elastic buffer on each lane for clock compensation; therefore, the latency is measured from the output of the elastic buffer until the octet appears on the receiver side GMII. As measured from a data octet output from the elastic buffer until that data appears on gmii_rxd[7:0] of the receiver side GMII of port 0, the latency through the core in the receive direction is six clock periods of userclk2 .