The registers provided are duplicated for each instance of the SGMII module in this core. The registers provided for SGMII operation in this core are adaptations of those defined in clauses 22 and 37 of the IEEE 802.3-2008 Specification [Ref 2] . In a QSGMII implementation, two different types of links exist. They are the QSGMII link between the MAC and PHY (QSGMII link) and the link across the Ethernet Medium itself (Medium). Information about the state of the QSGMII link is available in the registers that are described in this section.
The state of the link across the Ethernet Medium itself is not directly available when QSGMII Auto-Negotiation is not present. For this reason, the status of the link and the results of the PHYs Auto-Negotiation (for example, Speed and Duplex mode) must be obtained directly from the management interface of the connected PHY module. Registers at undefined addresses are read-only and return 0s.
|
Register Address |
Register Name |
|---|---|
|
0 |
SGMII Control register |
|
1 |
SGMII Status register |
|
2, 3 |
PHY Identifier |
|
15 |
SGMII Extended Status register |
|
18 |
SGMII Generic Control |