QSGMII Using Optional Auto-Negotiation - 4.0 English - PG029

The registers provided are duplicated for each instance of the SGMII module in this core. The registers are adaptations of those defined in clauses 22 and 37 of the IEEE 802.3-2008 Specification. In a QSGMII implementation, two different types of links exist. They are the QSGMII link between the MAC and PHY (QSGMII link) and the link across the Ethernet Medium itself (Medium).

Information regarding the state of both of these links is contained within the registers described in the following tables. Where applicable, the abbreviations QSGMII link and Medium are used in the register descriptions. Registers at undefined addresses are read-only and return 0s.