This module accepts received data from the QSGMII core. This data is sampled and sent out of the GMII receiver interface for the attached external PHY. The 1 Gbps and 100 Mbps cases are illustrated in This Figure .
At 1 Gbps the data is valid on every clock cycle of the 125 MHz reference clock ( clk125m ). Data received from the core is clocked straight through the Receiver Rate Adaptation module.
At 100 Mbps, the data is repeated for a 10 clock period duration of clk125m ; at 10 Mbps, the data is repeated for a 100 clock period duration of clk125m . The Receiver Rate Adaptation Module samples this data using the sgmii_clk_en clock enable. The lower half of the byte is sent on the LSB 4 bits of gmii_rxd_out[3:0] followed by the upper nibble. This operation is done on sgmii_ddr_clk_en .