QSGMII Core Physical Side Interface

QSGMII Core Physical Side Interface - 3.5 English

Quad Serial Gigabit Media Independent LogiCORE Product Guide (PG029)

Document ID

PG029

Release Date

2023-11-02

Version

3.5 English

Table: Transceiver Interface Pinout describes the interface to the device-specific transceiver. The core is connected to the chosen transceiver in the appropriate HDL example design delivered with the core.

Table 2-6: Transceiver Interface Pinout
Signal	Direction	Description
mgt_rx_reset ⁽¹⁾	Output	Reset signal issued by the core to the device-specific transceiver receiver path. Connects to the gtrxreset signal of the device-specific transceiver. This reset is a combination of hard reset, soft reset and reset due to rxbuffer errors.
mgt_tx_reset ⁽²⁾	Output	Reset signal issued by the core to the device-specific transceiver transmitter path. Connects to the gttxreset signal of the device-specific transceiver. This reset is a combination of hard reset, soft reset and reset due to txbuffer errors.
userclk	Input	Also connected to txusrclk of the device-specific transceiver. Clock domain is not applicable.
userclk2	Input	Also connected to txusrclk2 of the device-specific transceiver. Clock domain is not applicable.
rxrecclk	Input	Also connected to rxusrclk2 of the device-specific transceiver. Clock domain is not applicable.
dcm_locked	Input	A Digital Clock Manager (DCM) can be used to derive userclk and userclk2 . This is implemented in the HDL design example delivered with the core. The core uses this input to hold the device-specific transceiver in reset until the DCM obtains lock. Clock domain is not applicable.
reset_done	Input	Indicates that both transceiver transmit and receive paths have completed reset cycle.
rxchariscomma[3:0] ⁽¹⁾	Input	Connects to device-specific transceiver signal of the same name.
rxcharisk[3:0] ⁽¹⁾	Input	Connects to device-specific transceiver signal of the same name.
rxdata[31:0] ⁽¹⁾	Input	Connects to device-specific transceiver signal of the same name.
rxdisperr[3:0] ⁽¹⁾	Input	Connects to device-specific transceiver signal of the same name.
rxnotintable[3:0] ⁽¹⁾	Input	Connects to device-specific transceiver signal of the same name.
rxrundisp[3:0] ⁽¹⁾	Input	Connects to device-specific transceiver signal of the same name.
txbuferr ⁽²⁾	Input	Connects to device-specific transceiver signal of the sam e name.
powerdown ⁽²⁾	Output	Connects to device-specific transceiver signal of the same name.
txchardispmode[3:0] ⁽²⁾	Output	Connects to device-specific transceiver signal of the same name.
txchardispval[3:0] ⁽²⁾	Output	Connects to device-specific transceiver signal of the same name.
txcharisk[3:0] ⁽²⁾	Output	Connects to device-specific transceiver signal of the same name.
txdata[31:0] ⁽²⁾	Output	Connects to device-specific transceiver signal of the same name.
enablealign ⁽²⁾	Output	Connects to device-specific transceiver signal of the same name.
Notes: 1. When the core is used with a device-specific transceiver, rxrecclk is used as the 125 MHz reference clock for driving these signals. 2. When the core is used with a device-specific transceiver, userclk2 is used as the 125 MHz reference clock for driving these signals.