Table: QSGMII Block Physical Side Interface with Shared Logic in the Example Design
describes the interface to the device-specific transceiver for the case where shared logic is included in the example design. However,
Versal™ Adaptive SoC families only support
shared logic
i
s included in the example
design setting
.
Table 2-9:
QSGMII Block Physical Side Interface with Shared Logic in the Example Design
|
Signal
|
Direction
|
Description
|
|
gtrefclk
|
Input
|
125 MHz reference clock from IBUFDS to the transceiver
|
|
txp
|
Output
|
Transmit differential
|
|
txn
|
Output
|
Transmit differential
|
|
rxp
|
Input
|
Receive differential
|
|
rxn
|
Input
|
Receive differential
|
|
txoutclk
|
Output
|
txoutclk from transceiver
|
|
userclk
|
Input
|
Also connected to
txusrclk
of the device-specific transceiver. Clock domain is not applicable
|
|
userclk2
|
Input
|
Also connected to
txusrclk2
of the device-specific transceiver. Clock domain is not applicable.
|
|
rxoutclk
|
Output
|
rxoutclk
from transceiver.
|
|
rxuserclk
|
Input
|
Also connected to
rxusrclk
of the device-specific transceiver. Clock domain is not applicable.
|
|
rxuserclk2
|
Input
|
Also connected to
rxusrclk2
of the device-specific transceiver. Clock domain is not applicable.
|
|
independent_clock_bufg
|
Input
|
Stable clock used as stable clock in transceiver and also as control clock for IDELAYCTRL. This clock is 200 MHz for 7 series devices and 300 MHz for UltraScale+ families and UltraScale devices.
|
|
resetdone
|
Output
|
Indication that reset sequence of the transceiver is complete.
|
|
pma_reset
|
Input
|
Hard reset synchronized to
independent_clock_bufg
.
|
|
mmcm_locked
|
Input
|
Indication from the MMCM that the outputs are stable.
|
|
independent_clock_bufgdiv4
|
Input
|
Independent clock divided by 4. This clock is only present for UltraScale+ families and UltraScale devices when
Transceiver Control and Status Ports
are disabled.
|
|
GT Common Clock Interface
|
|
gt0_pll0outclk_in
|
Input
|
Valid only for Artix 7 families. Indicates out clock from PLL0 of GT Common.
|
|
gt0_pll0outrefclk_in
|
Input
|
Valid only for Artix 7 families. Indicates reference out clock from PLL0 of GT Common.
|
|
gt0_pll1outclk_in
|
Input
|
Valid only for Artix 7 families. Indicates out clock from PLL1 of GT Common.
|
|
gt0_pll1outrefclk_in
|
Input
|
Valid only for Artix 7 families. Indicates reference out clock from PLL1 of GT Common.
|
|
gt0_pll0lock_in
|
Input
|
Valid only for Artix 7 families. Indicates out PLL0 of GT Common has locked.
|
|
gt0_pll0refclklost_in
|
Input
|
Valid only for Artix 7 families. Indicates out reference clock for PLL0 of GT Common is lost.
|
|
gt0_pll0reset_out
|
Output
|
Valid only for Artix 7 families. Reset for PLL of GT Common from reset fsm in GT Wizard.
|
|
gt0_qplloutclk_in
|
Input
|
Valid only for non Artix 7 families. Indicates out clock from PLL of GT Common.
|
|
gt0_qplloutrefclk_in
|
Input
|
Valid only for non Artix 7 families. Indicates reference out clock from PLL of GT Common.
|
Table: QSGMII Block Physical Side Interface with Shared Logic in the Core
describes the interface to the device-specific transceiver when shared logic is in the core
Table 2-10:
QSGMII Block Physical Side Interface with Shared Logic in the Core
|
Signal
|
Direction
|
Description
|
|
gtrefclk_p
|
Input
|
125 MHz differential reference clock to IBUFDS
|
|
gtrefclk_p
|
Input
|
125 MHz differential reference clock to IBUFDS
|
|
gtrefclk_out
|
Output
|
125 MHz reference clock from IBUFDS
|
|
txp
|
Output
|
Transmit differential
|
|
txn
|
Output
|
Transmit differential
|
|
rxp
|
Input
|
Receive differential
|
|
rxn
|
Input
|
Receive differential
|
|
userclk_out
|
Output
|
Also connected to txusrclk of the device-specific transceiver. Clock domain is not applicable.
|
|
userclk2_out
|
Output
|
Also connected to txusrclk2 of the device-specific transceiver. Clock domain is not applicable.
|
|
rxuserclk_out
|
Output
|
Also connected to rxusrclk of the device-specific transceiver. Clock domain is not applicable.
|
|
rxuserclk2_out
|
Output
|
Also connected to rxusrclk2 of the device-specific transceiver. Clock domain is not applicable.
|
|
independent_clock_bufg
|
Input
|
Stable clock used as stable clock in transceiver and
also as control clock for IDELAYCTRL. This clock is 200 MHz for 7 series devices and 300 MHz for UltraScale+ families and UltraScale devices.
|
|
resetdone
|
Output
|
Indication that reset sequence of the transceiver is complete.
|
|
pma_reset_out
|
Output
|
Hard reset synchronized to
independent_clock_bufg
.
|
|
mmcm_locked_out
|
Output
|
Indication from the MMCM that the outputs are stable.
|
|
independent_clock_bufgdiv4_out
|
Output
|
Independent clock divided by 4. This clock is only present for UltraScale+ families and UltraScale devices when
Transceiver Control and Status Ports
are disabled.
|
|
GT Common Clock Interface
|
|
gt0_pll0outclk_out
|
Output
|
Valid only for Artix 7 families. Indicates out clock from PLL0 of GT Common.
|
|
gt0_pll0outrefclk_out
|
Output
|
Valid only for Artix 7 families. Indicates reference out clock from PLL0 of GT Common.
|
|
gt0_pll1outclk_out
|
Output
|
Valid only for Artix 7 families. Indicates out clock from PLL1 of GT Common.
|
|
gt0_pll1outrefclk_out
|
Output
|
Valid only for Artix 7 families. Indicates reference out clock from PLL1 of GT Common.
|
|
gt0_pll0lock_out
|
Output
|
Valid only for Artix 7 families. Indicates out PLL0 of GT Common has locked.
|
|
gt0_pll0refclklost_out
|
Output
|
Valid only for Artix 7 families. Indicates out reference clock for PLL0 of GT Common is lost.
|
|
gt0_qplloutclk_out
|
Output
|
Valid only for non Artix 7 families. Indicates out clock from PLL of GT Common.
|
|
gt0_qplloutrefclk_out
|
Output
|
Valid only for non Artix 7 families. Indicates reference out clock from PLL of GT Common.
|
.