An QSGMII adaptation module containing four instances of SGMII adaptation module. Each instance of SGMII adaptation module contains the following:
• The clock management logic required to enable the instance of SGMII operate at 10 Mbps, 100 Mbps, and 1 Gbps.
• GMII logic for both transmitter and receiver paths.
° In MAC mode the GMII style 8-bit interface is run at 125 MHz for 1 Gbps operation; 12.5 MHz for 100 Mbps operation; 1.25 MHz for 10 Mbps operation. The speed of operation is controlled by clock enables. The reference clock out ( sgmii_clk_chx ) is always 125 MHz.
° In PHY mode the GMII style 8-bit interface is run at 125 MHz for 1 Gbps operation; 25 MHz for 100 Mbps operation; 2.5 MHz for 10 Mbps operation. For 100/10 Mbps operation, LSB 4 bits of the GMII style interface is mapped to four bits of the MII.
The QSGMII Adaptation Module is described in the following files:
VHDL
<project_dir>/<component_name>/synth/qsgmii_adapt/
<component_name>_qsgmii_adapt.vhd
<component_name>_sgmii_adapt.vhd
<component_name>_clk_gen.vhd
<component_name>_clk_div.vhd
<component_name>_johnson_cntr.vhd
<component_name>_tx_rate_adapt.vhd
<component_name>_rx_rate_adapt.vhd
Verilog
<project_dir>/<component_name>/synth/qsgmii_adapt/
<component_name>_qsgmii_adapt.v
<component_name>_sgmii_adapt.v
<component_name>_clk_gen.v
<component_name>_clk_div.v
<component_name>_johnson_cntr.v
<component_name>_tx_rate_adapt.v
<component_name>_rx_rate_adapt.v
The GMII of the core always operates at 125 MHz. The core makes no differentiation between the three speeds of operation; it always effectively operates at 1 Gbps. However, at 100 Mbps, every data byte run through the core should be repeated 10 times to achieve the required bit rate; at 10 Mbps, each data byte run through the core should be repeated 100 times to achieve the required bit rate. Dealing with this repetition of bytes is the function of the SGMII adaptation module and its component blocks.