Problems in Obtaining a Link (Auto-Negotiation Disabled) - 3.5 English

Quad Serial Gigabit Media Independent LogiCORE Product Guide (PG029)

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Determine whether the device has successfully obtained a link with its link partner by doing the following:

Reading bit 1.2, Link Status, in MDIO register 1: Status register using the optional MDIO management interface (or look at status_vector_chx[1] ).

Monitoring the state of status_vector_chx[0] . If this is logic 1, then synchronization, and therefore a link, has been established. See Bit[0]: Link Status.

If the devices have failed to form a link then do the following:

Ensure that Auto-Negotiation is disabled in both the core and in the link partner (the device or test equipment connected to the core).

Monitor the state of the signal_detect signal input to the core. This should either be:

° Connected to an optical module to detect the presence of light. Logic 1 indicates that the optical module is correctly detecting light; logic 0 indicates a fault. Therefore, ensure that this is driven with the correct polarity.

° Signal must be tied to logic 1 (if not connected to an optical module).

Note: When signal_detect is set to logic 0, this forces the receiver synchronization state machine of the core to remain in the loss of sync state.

° See Problems with a High Bit Error Rate in a subsequent section.

When using a device-specific transceiver, perform these additional checks:

Ensure that the polarities of the txn/txp and rxn/rxp lines are not reversed. If they are, this can be fixed by using the txpolarity and rxpolarity ports of the device-specific transceiver.

Check that the device-specific transceiver is not being held in reset by monitoring the mgt_tx_reset and mgt_rx_reset signals between the core and the device-specific transceiver. If these are asserted, this indicates that the PMA Phase-Locked Loop (PLL) circuitry in the device-specific transceiver has not obtained lock; check the PLL Lock signals output from the device-specific transceiver.