Ports Added - 3.5 English

rxoutclk

Output

rxoutclk from the Transceiver

This was previously connected internally to clocking elements and routed to rxuserclk and rxuserclk2 .

This can be left open if rxoutclk can be shared across instances or if not should drive clocking elements.

rxuserclk

Input

Signal from the shared logic block to the transceiver

If rxoutclk can be shared across instances, connect O/P of shared logic block. If not connect to rxoutclk after passing through additional clocking elements.

rxuserclk2

Input

Signal from the shared logic block to the transceiver

If rxoutclk can be shared across instances, connect O/P of shared logic block. If not connect to rxoutclk after passing through additional clocking elements.

gt0_pll0outclk_in

Input

Valid only for AMD Artix ™ 7 families. Indicates out clock from PLL0 of GT Common.

Should be connected to signal of same name from GT Common

gt0_pll0outrefclk_in

Input

Valid only for Artix 7 families. Indicates reference out clock from PLL0 of GT Common.

Should be connected to signal of same name from GT Common

gt0_pll1outclk_in

Input

Valid only for Artix 7 families. Indicates out clock from PLL1 of GT Common.

Should be connected to signal of same name from GT Common

gt0_pll1outrefclk_in

Input

Valid only for Artix 7 families. Indicates reference out clock from PLL1 of GT Common.

Should be connected to signal of same name from GT Common

gt0_pll0lock_in

Input

Valid only for Artix 7 families. Indicates out PLL0 of GT Common has locked.

Should be connected to signal of same name from GT Common

gt0_pll0refclklost_in

Input

Valid only for Artix 7 families. Indicates out reference clock for PLL0 of GT Common is lost.

Should be connected to signal of same name from GT Common

gt0_pll0reset_out

output

Valid only for Artix 7 families. Reset for PLL of GT Common from reset fsm in GT Wizard

Should be connected to signal of same name from GT Common or can be left open if not needed

gt0_qplloutclk_in

Input

Valid only for non Artix 7 families. Indicates out clock from PLL of GT Common.

Should be connected to signal of same name from GT Common

gt0_qplloutrefclk_in

Input

Valid only for non Artix 7

Families. Indicates reference out clock from PLL of GT Common.

Should be connected to signal of same name from GT Common

gt0_rxchariscomma_out[3:0]

Output

RX Character is Comma indication

If you want to be more compatible with the previous version of the core and also if DRP interface was not used, do not request the Transceiver Debug feature.

gt0_rxcharisk_out[3:0]

Output

RX Character is K indication

gt0_rxbyteisaligned_out

Output

RX Byte is aligned indication

gt0_rxbyterealign_out

Output

Rx Byte is realigned indication

gt0_rxcommadet_out

Output

RX Comma is detected indication

gt0_txpolarity

Input

Switch the sense of the TXN/P pins

If you want to be more compatible with the previous version of the core and also if DRP interface was not used, do not request the Transceiver Debug feature. Otherwise, drive this signal according to the relevant transceiver user guide.

gt0_txdiffctrl[3:0]

Input

Can be used to tune the transceiver TX waveform

gt0_txprecursor[4:0]

Input

Can be used to tune the transceiver TX waveform

gt0_txpostcursor[4:0]

Input

Can be used to tune the transceiver TX waveform

gt0_rxpolarity

Input

Switch the sense of the RXN/P pins

gt0_txprbssel_in[2:0]

Input

TX Pattern Generator control signals to test signal integrity

gt0_txprbsforceerr_in

Input

TX Pattern Generator control signals to test signal integrity

gt0_rxprbscntreset_in

Input

RX Pattern Checker reset

gt0_rxprbserr_out

Output

RX Pattern Checker error output

gt0_rxprbssel_in[2:0]

Input

RX Pattern Checker control signals to test signal integrity

gt0_loopback_in[2:0]

Input

Loopback within transceiver

gt0_txresetdone_out

Output

Transmitter Reset Done

gt0_rxresetdone_out

Output

Receiver Reset Done

gt0_rxdisperr_out[3:0]

Output

Indicates there is disparity error in received data

gt0_rxnotintable_out[3:0]

Output

Indicates received 10 bit pattern was not found in 8B/10B decode table

gt0_eyescanreset

Input

Reset the EYE Scan logic

gt0_eyescantrigger

Input

Trigger the EYE Scan logic

gt0_eyescandataerror

Output

Signals an error during Eye Scan

gt0_rxrate[2:0]

Input

Change the PLL Divider value

gt0_rxcdrhold

Input

Freeze the CDR loop

gt0_rxcdrlock_out

Output

CDR loop has locked

gt0_rxratedone_out

Output

Asserted in response to change in RXRATE

gt0_rxlpmhfhold_in

Input

GTP Low power mode signal

gt0_rxlpmlfhold_in

Input

GTP Low power mode signal

gt0_rxmonitorout_out[6:0]

Output

GTX/GTH RX DFE Signal

gt0_rxmonitorsel_in[1:0]

Input

GTX/GTH RX DFE Signal