Port Descriptions - 4.0 English - PG029

Quad Serial Gigabit Media Independent LogiCORE IP Product Guide (PG029)
Document ID
PG029
Release Date
2025-12-09
Version
4.0 English

Internal Encrypted Hierarchy of the Core Level Ports

All ports in the encrypted hierarchy of the core are internal connections in FPGA logic. Un-encrypted HDL in the core and example design (delivered with the core) connect the core, where appropriate, to a device-specific transceiver, and/or add IBUFs, OBUFs, and IOB flip-flops to the external signals of the GMII/MII. IOBs are added to the remaining unconnected ports to take the example design through the AMD implementation software. All the ports described here indicate the pins at the in the encrypted hierarchy of the core level. The block level design instantiates the core and transceiver.

All clock management logic is placed in this example design, allowing you more flexibility in implementation (such as designs using multiple cores). This example design is provided in both VHDL and Verilog.

The following figure shows the pinout for the QSGMII core using a device-specific transceiver with the optional MDIO Management and optional Auto-Negotiation.

The port name for multiple instances of an interface is generalized as CHx. CHx takes the value CH0, CH1, CH2, and CH3.

Figure 1. Component Pinout of QSGMII Core with Optional MDIO and Auto-Negotiation

The following figure shows the pinout for the QSGMII core using a device-specific transceiver with only the optional MDIO Management. The port name for multiple instances of an interface is generalized as CHx. CHx takes the value CH0, CH1, CH2, and CH3.

Figure 2. Component Pinout of QSGMII Core with Only Optional MDIO Management

The following figure shows the pinout for the QSGMII core using a device-specific transceiver with only the optional Auto-Negotiation.

The port name for multiple instances of an interface is generalized as CHx. CHx takes the value CH0, CH1, CH2, and CH3

.
Figure 3. Component Pinout of QSGMII Core with Only Optional Auto-Negotiation

The following figure shows the pinout for the QSGMII core using a device-specific transceiver with only the optional Auto-Negotiation.

The port name for multiple instances of an interface is generalized as CHx. CHx takes the value CH0, CH1, CH2, and CH3.

Figure 4. Component Pinout for QSGMII Core without Optional MDIO or Auto-Negotiation

QSGMII Core Client Side Interface

This interface contains four groups of interfaces, with each group containing a set of the GMII interface, the optional management interface if supported and configuration vectors. MII interface, if present on the QSGMII block, is converted to a GMII type interface. The interfaces end in chx, taking the values ch0 to ch3, indicating the port connection to the respective GMII interface.

GMII Pinout

The following table describes the GMII-side interface signals of the core that are common to all parameterizations of the core. These are typically attached to an Ethernet MAC, either off-chip or internally integrated. The HDL block level in PHY mode of operation for seamless connection to pads in IP Canvas delivered with the core connects these signals to IOBs to provide a place-and-route example.

Table 1. GMII Interface Signals Pinout
Signal Direction Description
gmii_txd_chx[7:0] 1 Input GMII Transmit data from MAC
gmii_tx_en_chx 1 Input GMII Transmit control signal from MAC
gmii_tx_er_chx 1 Input GMII Transmit control signal from MAC
gmii_rxd_chx[7:0]1 Output GMII Received data to MAC
gmii_rx_dv_chx1 Output GMII Received control signal to MAC
gmii_rx_er_chx1 Output GMII Received control signal to MAC
gmii_isolate_chx1 Output IOB 3-state control for GMII Isolation. Only of use when implementing an external GMII.
  1. These signals are synchronous to the internal 125 MHz reference clock of the core. This is userclk2.

Common Signals

The following table describes the remaining signals common to all parameterizations of the core.

Table 2. Other Common Signals
Signal Direction Description
reset Input Asynchronous reset for the entire core. Active-High. Clock domain is not applicable.
signal_detect Input Signal direct from the Physical Medium Dependent (PMD) sublayer indicating the presence of light detected at the optical receiver. If set to 1, indicates that the optical receiver has detected light. If set to 0, this indicates the absence of light. If unused, this signal should be set to 1 to enable correct operation the core. Clock domain is not applicable.

MDIO Management Interface Pinout (Optional)

The optional MDIO Management Interface is provided for each instance of SGMII. The chx suffix denotes a generic nomenclature for describing the interface. Each of the interfaces are identified with chx taking values from ch0 to ch3.

The following table describes the optional MDIO interface signals of the core that are used to access the PCS Management registers. Each of these interfaces is typically connected to the MDIO port of a MAC device, either off-chip or to an internally integrated MAC core. For more information, see Management Registers.

Table 3. Optional MDIO Interface Pinout
Signal Direction Clock Domain Description
mdc_chx Input NA Management clock (<= 2.5 MHz).
mdio_in_chx 1 Input mdc_chx Input data signal for communication with the instance number x of the MDIO controller (for example, an Ethernet MAC). Tie High if unused.
mdio_out_chx 1 Output mdc_chx Output data signal for communication with the instance number x of the MDIO controller (for example, an Ethernet MAC).
mdio_tri_chx 1 Output mdc_chx 3-state control for MDIO signals. The value 0 signals that the value on mdio_out should be asserted onto the MDIO interface.
phyad_chx[4:0] Input NA Physical Addresses of the PCS Management register set of each x instance of SGMII. It is expected that this signal is tied off to a logical value.
  1. These signals can be connected to a 3-state buffer to create a bidirectional mdio signal suitable for connection to an external MDIO controller (for example, an Ethernet MAC).

Auto-Negotiation Interface Pinout (Optional)

The following table describes the signals present when the optional Auto-Negotiation functionality is present.
Table 4. Optional Auto-Negotiation Interface Signal Pinout
Signal Direction Description
an_interrupt_chx 1 Output

When an optional management interface is present, active-High interrupt to signal the completion of an Auto-Negotiation cycle. This interrupt can be enabled/disabled and cleared by writing to the appropriate PCS Management register.

When an optional management interface is not present, this signal indicates the completion of the Auto-Negotiation cycle. Is reset automatically if Auto-Negotiation restarts. This bit cannot be cleared.
  1. These signals are synchronous to the internal 125 MHz reference clock of the core. This is userclk2 when the core is used with the device-specific transceiver.

Additional Configuration Interface

This interface can be used over and above the optional management interface to write into the Control register (Register 0) and the Auto-Negotiation Advertisement register (Register 4).

Table 5. Additional Configuration Interface Signal Pinout
Signal Direction Description
configuration_vector_chx[5:0] 1 Input

Bit[0]:Unidirectional Enable

When set to 1, Enable Transmit irrespective of the state of RX. When set to 0, Normal operation

Bit[1]: Reserved

Bit[2]: Power Down

When set to 1, the device-specific transceiver is placed in a low-power state. A reset must be applied to clear.

This bit is valid only on configuration_vector_ch0 and is reserved in other instances of configuration_vector.

Bit[3] Isolate

When set to 1, the GMII should be electrically isolated. When set to 0, normal operation is enabled

Bit[4] Auto-Negotiation Enable

This signal is valid only if the Auto-Negotiation (AN) module is enabled through the AMD Vivado™ IP catalog. When set to 1, the signal enables the AN feature. When set to 0, AN is disabled.

Bit[5] gt_channel_valid

This signal is valid only for 7 series devices. This enables the contribution of status_vector_chx[1] signal towards the generation of data valid for GT RX FSM. This signal should be enabled based on the channel validity.
configuration_vector_valid_chx 1 Input This signal is valid only when the MDIO interface is present. The rising edge of this signal is the enable signal to overwrite the Register 0 contents that were written from the MDIO interface. For triggering a fresh update of Register 0 through configuration_vector_chx, this signal should be deasserted and then reasserted.
an_adv_config_vector_chx[15:0] 1 Input

QSGMII operating in MAC Mode, the AN_ADV register is hard wired internally to "0x0001" and this bus has no effect. For QSGMII operating in PHY mode, the AN_ADV register is programmed by this bus as specified for the following bits.

Bit[0]: Always 1

Bits [9:1]: Reserved

Bits [11:10]: Speed

1 1 Reserved

1 0 1000 Mb/s

0 1 100 Mb/s

0 0 10 Mb/s

Bits [12]:Duplex Mode

1 Full Duplex

0 Half Duplex

Bit[13]: Reserved

Bit [14]: Acknowledge

Bit [15]: PHY Link Status

1 Link Up

0 Link Down
an_adv_config_valid_chx 1 Input This signal is valid only when the MDIO interface is present. The rising edge of this signal is the enable signal to overwrite the Register 4 contents that were written from the MDIO interface. For triggering a fresh update of Register 4 through an_adv_config_vector_chx, this signal should be deasserted and then reasserted.
an_restart_config_chx 1 Input This signal is valid only when AN is present. The rising edge of this signal is the enable signal to overwrite Bit 9 of Register 0. For triggering a fresh AN Start, this signal should be deasserted and then reasserted.
status_vector_chx[15:0] 1 Output

Bit[0]: Link Status

This signal indicates the status of the link. When High, the link is valid; synchronization of the link has been obtained and Auto-Negotiation (if present and enabled) has successfully completed. When Low, a valid link has not been established. Either link synchronization has failed or Auto-Negotiation (if present and enabled) has failed to complete.

When auto-negotiation is enabled, this signal is identical to Status register Bit 1.2: Link Status.

When auto-negotiation is disabled, this signal is identical to status_vector_chx Bit[1].

Bit[1]: Link Synchronization

This signal indicates the state of the synchronization state machine (IEEE 802.3 figure 36-9) which is based on the reception of valid 8B/10B code groups. This signal is similar to Bit[0] (Link Status), but is not qualified with Auto-Negotiation.

When High, link synchronization has been obtained and in the synchronization state machine, sync_status=OK.

When Low, synchronization has failed.

Bit[2]: RUDI(/C/)

The core is receiving /C/ ordered sets (Auto-Negotiation Configuration sequences).

Bit[3]: RUDI(/I/)

The core is receiving /I/ ordered sets (Idles).

Bit[4]: RUDI(INVALID)

The core has received invalid data while receiving/C/ or /I/ ordered set.

Bit[5]: RXDISPERR

The core has received a running disparity error during the 8B/10B decoding function.

Bit[6]: RXNOTINTABLE

The core has received a code group that is not recognized from the 8B/10B coding tables.
status_vector_chx[15:0] 1 Output

Bit[7]: PHY Link Status

This bit represents the link status of the external PHY device attached to the other end of the QSGMII link (High indicates that the PHY has obtained a link with its link partner; Low indicates that is has not linked with its link partner.)

Bit[9:8]: Remote Fault Encoding

This signal indicates the remote fault encoding (IEEE 802.3 table 37-3). This signal is validated by bit 13 of the status_vector_chx and is only valid when Auto-Negotiation is enabled.

This signal has no significance when the core is in PHY mode and indicates "00."

Bit [11:10]: SPEED

This signal indicates that the speed is negotiated and is only valid when Auto-Negotiation is enabled. The signal encoding follows:

Bit[11] Bit[10]

1 1 Reserved

1 0 1000 Mb/s

0 1 100 Mb/s

0 0 10 Mb/s

Bit[12]: Duplex Mode

This bit indicates the Duplex mode negotiated with the link partner.

1 = Full Duplex

0 = Half Duplex

Bit[13] Remote Fault

When this bit is logic 1, it indicates that a remote fault is detected and the type of remote fault is indicated by status_vector_chx bits[9:8].

This bit is only deasserted when an MDIO read is made to status register (register 1). This signal has no significance in QSGMII PHY mode

Bits[15;14]: Pause

These bits reflect the bits [8:7] of Register 5 (Link Partner Base AN register).

Bit[15] Bit[14]

0 0 No Pause

0 1 Symmetric Pause

1 0 Asymmetric Pause towards Link partner

1 1 Both Symmetric Pause and Asymmetric Pause towards link partner
  1. Signals are synchronous to the core internal 125 MHz reference clock userclk2 when used with a device-specific transceiver.

QSGMII Core Physical Side Interface

The following table describes the interface to the device-specific transceiver. The core is connected to the chosen transceiver in the appropriate HDL example design delivered with the core.

Table 6. Transceiver Interface Pinout
Signal Direction Description
mgt_rx_reset 1 Output Reset signal issued by the core to the device-specific transceiver receiver path. Connects to the gtrxreset signal of the device-specific transceiver. This reset is a combination of hard reset, soft reset and reset due to rxbuffer errors.
mgt_tx_reset 2 Output Reset signal issued by the core to the device-specific transceiver transmitter path. Connects to the gttxreset signal of the device-specific transceiver. This reset is a combination of hard reset, soft reset and reset due to txbuffer errors.
userclk Input Also connected to txusrclk of the device-specific transceiver. Clock domain is not applicable.
userclk2 Input Also connected to txusrclk2 of the device-specific transceiver. Clock domain is not applicable.
rxrecclk Input Also connected to rxusrclk2 of the device-specific transceiver. Clock domain is not applicable.
dcm_locked Input A Digital Clock Manager (DCM) can be used to derive userclk and userclk2. This is implemented in the HDL design example delivered with the core. The core uses this input to hold the device-specific transceiver in reset until the DCM obtains lock. Clock domain is not applicable.
reset_done Input Indicates that both transceiver transmit and receive paths have completed reset cycle.
rxchariscomma[3:0] 1 1 Input Connects to device-specific transceiver signal of the same name.
rxcharisk[3:0] Input Connects to device-specific transceiver signal of the same name.
rxdata[31:0] 1 Input Connects to device-specific transceiver signal of the same name.
rxdisperr[3:0] 1 Input Connects to device-specific transceiver signal of the same name.
rxnotintable[3:0] 1 Input Connects to device-specific transceiver signal of the same name.
rxrundisp[3:0] 1 Input Connects to device-specific transceiver signal of the same name.
txbuferr 2 Input Connects to device-specific transceiver signal of the sam e name.
powerdown 2 Output Connects to device-specific transceiver signal of the same name.
txchardispmode[3:0] 2 Output Connects to device-specific transceiver signal of the same name.
txchardispval[3:0] 2 Output Connects to device-specific transceiver signal of the same name.
txcharisk[3:0] 2 Output Connects to device-specific transceiver signal of the same name.
txdata[31:0] 2 Output Connects to device-specific transceiver signal of the same name.
enablealign 2 Output Connects to device-specific transceiver signal of the same name.
  1. When the core is used with a device-specific transceiver, rxrecclk is used as the 125 MHz reference clock for driving these signals.
  2. When the core is used with a device-specific transceiver, userclk2 is used as the 125 MHz reference clock for driving these signals.

Block Hierarchy Level Ports

All the ports described here indicate the pins at the block level. The block level design instantiates the core and transceiver. The block level design is expected to be pulled from the IP catalog into the IP Canvas.

The following table shows the pinout for the QSGMII block with the optional MDIO Management and optional Auto-Negotiation. The port name for multiple instances of an interface is generalized as "CHx." "CHx" takes the value "CH0," "CH1," "CH2," and "CH3."

Figure 5. Component Pinout of QSGMII Block with Optional MDIO and Auto-Negotiation

The following diagram shows the pinout for the QSGMII block with only optional MDIO Management. The port name for multiple instances of an interface is generalized as "CHx." "CHx" takes the value "CH0," "CH1," "CH2," and "CH3."

Figure 6. Component Pinout of QSGMII Block with Only Optional MDIO Management

The following figure shows the pinout for the QSGMII block with only optional Auto-Negotiation. The port name for multiple instances of an interface is generalized as "CHx." "CHx" takes the value "CH0," "CH1," "CH2," and "CH3."

Figure 7. Component Pinout of QSGMII Block with Only Optional Auto-Negotiation

The following diagram shows the pinout for the QSGMII block without optional MDIO or Auto-Negotiation. The port name for multiple instances of an interface is generalized as "CHx." "CHx" takes the value "CH0," "CH1," "CH2," and "CH3."

Figure 8. Component Pinout of QSGMII Block without Optional MDIO or Auto-Negotiation

QSGMII Block Client Side Interface

This interface contains four groups of interfaces, with each group containing a set of the GMII/MII interface, the optional management interface if supported and configuration vectors. The interfaces end in "chx," taking the values ch0 to ch3, indicating the port connection to the respective GMII interface.

GMII Pinout

This interface is enabled in the MAC mode or GMII configuration of PHY mode. In the MAC mode this interface is expected to be connected to the GMII interface of Tri-Mode Ethernet MAC core (TEMAC). In the GMII configuration of PHY mode, this interface is brought out onto the pads.

Table 7. GMII Interface Signals Pinout
Signal Direction Description
gmii_txd_chx[7:0] 1 Input GMII Transmit data
gmii_txd_en_chx 1 Input GMII Transmit data enable
gmii_tx_er_chx 1 Input GMII Transmit error
gmii_rxd_chx[7:0] 2 Output GMII Receive data
gmii_rxd_dv_chx 2 Output GMII Receive data valid
gmii_rx_er_chx 2 Output GMII Receive error
gtx_clk_chx Input GMII TX clock. This is valid only in GMII configuration in PHY mode
gmii_rx_clk_chx Output GMII RX clock. This is valid only in GMII configuration in PHY mode
sgmii_clk_en_chx Output Clock enables. This valid only in MAC mode.
sgmii_clk_en_rx_chx Output Clock enables. This valid only in MAC mode and when RX path is on rxuserclk2.
  1. In MAC mode these signals are synchronous to 125 MHz reference clock of the core, that is, userclk2. In GMII configuration of PHY mode these signals are synchronous to gtx_clk_chx and these signals are synchronized to userclk2 domain using Transmit Elastic Buffer present in the block
  2. These signals are synchronous to 125 MHz reference clock of the core. This is userclk2.
Table 8. MII Interface Signals Pinout
Signal Direction Description
mii_txd_chx[7:0] 1 Input MII Transmit data
mii_tx_en_chx 1 Input MII Transmit data enable
mii_tx_er_chx 1 Input MII Transmit error
mii_rxd_chx[7:0] 2 Output MII Receive data
mii_rx_dv_chx 2 Output MII Receive data valid
mii_rx_er_chx 2 Output MII Receive data error
mii_tx_clk_chx Output MII TX clock. This is valid only in MII configuration in MII mode. The clock can be 2.5/25 MHz based on 10/100 Mb/s mode of operation
mii_rx_clk_chx Output MII RX clock. This is valid only in MII configuration in MII mode. The clock can be 2.5/25 MHz based on 10/100 Mb/s mode of operation
  1. These signals should be driven on ii_tx_clk_chx.
  2. These signals are synchronous to mii_rx_clk_chx.

Common Signals

See Table 2 for these signals.

MDIO Management Interface Pinout (Optional)

See of Table 3 for these signals.

Auto-Negotiation Interface Pinout (Optional)

See Table 4 for these signals.

Additional Configuration Interface

See Table 5 for these signals.

QSGMII Block Physical Side Interface

The following table describes the interface to the device-specific transceiver for the case where shared logic is included in the example design. However, Versal Adaptive SoC families only support shared logic is included in the example design setting.

Table 9. QSGMII Block Physical Side Interface with Shared Logic in the Example Design
Signal Direction Description
gtrefclk Input 125 MHz reference clock from IBUFDS to the transceiver
txp Output Transmit differential
txn Output Transmit differential
rxp Input Receive differential
rxn Input Receive differential
txoutclk Output txoutclk from transceiver
userclk Input Also connected to txusrclk of the device-specific transceiver. Clock domain is not applicable
userclk2 Input Also connected to txusrclk2 of the device-specific transceiver. Clock domain is not applicable.
rxoutclk Output rxoutclk from transceiver.
rxuserclk Input Also connected to rxusrclk of the device-specific transceiver. Clock domain is not applicable.
rxuserclk2 Input Also connected to rxusrclk2 of the device-specific transceiver. Clock domain is not applicable.
independent_clock_bufg Input Stable clock used as stable clock in transceiver and also as control clock for IDELAYCTRL. This clock is 200 MHz for devices and 300 MHz for UltraScale+ families and UltraScale devices.
resetdone Output Indication that reset sequence of the transceiver is complete.
pma_reset Input Hard reset synchronized to independent_clock_bufg .
mmcm_locked Input Indication from the MMCM that the outputs are stable.
independent_clock_bufgdiv4 Input Independent clock divided by 4. This clock is only present for UltraScale+ families and UltraScale devices when Transceiver Control and Status Ports are disabled.
GT Common Clock Interface
gt0_pll0outclk_in Input Valid only for Artix 7 families. Indicates out clock from PLL0 of GT Common.
gt0_pll0outrefclk_in Input Valid only for Artix 7 families. Indicates reference out clock from PLL0 of GT Common.
gt0_pll1outclk_in Input Valid only for Artix 7 families. Indicates out clock from PLL1 of GT Common.
gt0_pll1outrefclk_in Input Valid only for AMD Artix™ 7 families. Indicates reference out clock from PLL1 of GT Common.
gt0_pll0lock_in Input Valid only for Artix 7 families. Indicates out PLL0 of GT Common has locked.
gt0_pll0refclklost_in Input Valid only for Artix 7 families. Indicates out reference clock for PLL0 of GT Common is lost.
gt0_pll0reset_out Output Valid only for Artix 7 families. Reset for PLL of GT Common from reset fsm in GT Wizard.
gt0_qplloutclk_in Input Valid only for non Artix 7 families. Indicates out clock from PLL of GT Common.
gt0_qplloutrefclk_in Input Valid only for non Artix 7 families. Indicates reference out clock from PLL of GT Common.

The following table describes the interface to the device-specific transceiver when shared logic is in the core.

Table 10. QSGMII Block Physical Side Interface with Shared Logic in the Core
Signal Direction Description
gtrefclk_p Input 125 MHz differential reference clock to IBUFDS
gtrefclk_p Input 125 MHz differential reference clock to IBUFDS
gtrefclk_out Output 125 MHz reference clock from IBUFDS
txp Output Transmit differential
txn Output Transmit differential
rxp Input Receive differential
rxn Input Receive differential
userclk_out Output Also connected to txusrclk of the device-specific transceiver. Clock domain is not applicable.
userclk2_out Output Also connected to txusrclk2 of the device-specific transceiver. Clock domain is not applicable.
rxuserclk_out Output Also connected to rxusrclk of the device-specific transceiver. Clock domain is not applicable.
rxuserclk2_out Output Also connected to rxusrclk2 of the device-specific transceiver. Clock domain is not applicable.
independent_clock_bufg Input

Stable clock used as stable clock in transceiver and also as control clock for IDELAYCTRL. This clock is 200 MHz for 7 series devices and 300 MHz for UltraScale+ families and UltraScale devices.
resetdone Output Indication that reset sequence of the transceiver is complete.
pma_reset_out Output Hard reset synchronized to independent_clock_bufg.
mmcm_locked_out Output Indication from the MMCM that the outputs are stable.
independent_clock_bufgdiv4_out Output Independent clock divided by 4. This clock is only present for UltraScale+ families and UltraScale devices when Transceiver Control and Status Ports are disabled.
GT Common Clock Interface
gt0_pll0outclk_out Output Valid only for Artix 7 families. Indicates out clock from PLL0 of GT Common.
gt0_pll0outrefclk_out Output Valid only for Artix 7 families. Indicates reference out clock from PLL0 of GT Common.
gt0_pll1outclk_out Output Valid only for Artix 7 families. Indicates out clock from PLL1 of GT Common.
gt0_pll1outrefclk_out Output Valid only for Artix 7 families. Indicates reference out clock from PLL1 of GT Common.
gt0_pll0lock_out Output Valid only for Artix 7 families. Indicates out PLL0 of GT Common has locked.
gt0_pll0refclklost_out Output Valid only for Artix 7 families. Indicates out reference clock for PLL0 of GT Common is lost.
gt0_qplloutclk_out Output Valid only for non Artix 7 families. Indicates out clock from PLL of GT Common.
gt0_qplloutrefclk_out Output Valid only for non Artix 7 families. Indicates reference out clock from PLL of GT Common.