Port Changes from v2.0 to v3.0 - 3.5 English - PG029

Quad Serial Gigabit Media Independent LogiCORE Product Guide (PG029)

Document ID: PG029
Release Date: 2023-11-02
Version: 3.5 English

Quad Serial Gigabit Media Independent v3.5 LogiCORE IP Product Guide
IP Facts
Introduction
Features
Overview
Navigating Content by Design Process
Core Overview
System Overview
SGMII
GMII/MII Block
PCS Transmit Engine
PCS Receive Engine and Synchronization
Optional Auto-Negotiation Block
Optional PCS Management Registers
Aggregator
Aligner
Transceiver Interface Block
Elastic Buffer
Feature Summary
Applications
QSGMII MAC
QSGMII PHY
Licensing and Ordering
Product Specification
Standards
Performance
Latency
Transmit Path Latency
Receive Path Latency
Throughput
Resource Utilization
Port Descriptions
Internal Encrypted Hierarchy of the Core Level Ports
QSGMII Core Client Side Interface
GMII Pinout
Common Signals
MDIO Management Interface Pinout (Optional)
Auto-Negotiation Interface Pinout (Optional)
Additional Configuration Interface
QSGMII Core Physical Side Interface
Block Hierarchy Level Ports
QSGMII Block Client Side Interface
GMII Pinout
Common Signals
MDIO Management Interface Pinout (Optional)
Auto-Negotiation Interface Pinout (Optional)
Additional Configuration Interface
QSGMII Block Physical Side Interface
Transceiver Control and Status Ports
Register Space
MDIO Management System
MDIO Bus System
MDIO Transactions
Write Transaction
Read Transaction
MDIO Addressing
Physical Address (PHYAD)
Register Address (REGAD)
Connecting the MDIO to an Internally Integrated STA
Connecting the MDIO to an External STA
Management Registers
QSGMII Using Optional Auto-Negotiation
Register 0: SGMII Control Register
Register 1: SGMII Status Register
Link Status
Registers 2 and 3 (PHY IDENTIFIER)
Register 4: SGMII Auto-Negotiation Advertisement
Register 5: SGMII Auto-Negotiation Link Partner Ability
Register 6: SGMII Auto-Negotiation Expansion
Register 7: SGMII Auto-Negotiation Next Page Transmit
Register 8: SGMII Next Page Receive
Register 15: SGMII Extended Status
Register 16: SGMII Auto-Negotiation Interrupt Control
Register 18: SGMII Generic Control
QSGMII Without Optional Auto-Negotiation
Register 0: SGMII Control Register
Register 1: SGMII Status Register
Link Status
Registers 2 and 3 (PHY IDENTIFIER)
Register 15: SGMII Extended Status
Register 18: SGMII Generic Control (Register 18)
Designing with the Core
Design Guidelines
Understand the Core Netlist Features and Interfaces
Customize and Generate the Core
Examine the Example Design
Implement the QSGMII Core in Your Application
Write an HDL Application
Synthesize your Design and Create a Bitstream
Simulate and Download your Design
Know the Degree of Difficulty
Keep it Registered
Recognize Timing Critical Signals
Make Only Allowed Modifications
Shared Logic
Clocking
Resets
Using the Client Side GMII/MII Datapath
Using the Encrypted Core Level Client-Side GMII/MII
GMII Transmission
Normal Frame Transmission
Error Propagation
GMII Reception
Normal Frame Reception
Normal Frame Reception with Extension Field
Frame Reception with Errors
MII Transmission
100 Mbps Frame Transmission
10 Mbps Frame Transmission
MII Reception
100 Mbps Frame Reception
10 Mbps Frame Reception
Additional Client-Side QSGMII Adaptation Logic
QSGMII Adaptation Module Top-Level
SGMII Adaptation Module Top-Level
Transmitter Rate Adaptation Module
QSGMII Operating in MAC Mode
QSGMII Operating in PHY Mode
Receiver Rate Adaptation Module
QSGMII Operating in MAC Mode
QSGMII Operating in PHY Mode
Clock Generation Module
Using the Transceiver
Transceiver Logic
Virtex 7 Devices
Zynq 7000 SoC/Kintex 7 Devices
Artix 7 Devices
UltraScale and UltraScale+ Devices
Clock Sharing Across Multiple Cores with Transceivers
Virtex 7 Devices
Zynq 7000 SoC and Kintex 7 Devices
Artix 7 Devices
UltraScale and UltraScale+ Devices
Design Flow Steps
Customizing and Generating the Core
Core Customization Vivado IDE
Select Interface Vivado IDE
Shared Logic Options in Vivado IDE
User Parameters
Output Generation
Examples
Examples Simulation
Synthesis
Simulation
Instantiation Template
Miscellaneous
Constraining the Core
Device, Package, and Speed Grade Selections
I/O Location Constraints
Placement Constraints
Transceiver Placement
Versal GTY Transceivers
Transceiver Placement Constraint
Clock Period Constraints
Virtex 7 FPGA GTH Transceivers
Transceiver Placement Constraint
Clock Period Constraints
GTH Transceiver Attributes
Virtex 7 FPGA GTX Transceivers
Transceiver Placement Constraint
Clock Period Constraints
GTX Transceiver Attributes
Zynq 7000 SoC and Kintex 7 FPGA GTX Transceivers
Transceiver Placement Constraint
Clock Period Constraints
GTX Transceiver Attributes
Artix 7 FPGA GTP Transceivers
Transceiver Placement Constraint
Clock Period Constraints
GTP Transceiver Attributes
Constraints When Using External GMII/MII
Clock Period Constraints
GMII/MII IOB Constraints
GMII Input Setup/Hold Timing
Zynq 7000 SoC, Virtex 7, Kintex 7, and Artix 7 Devices
Simulation
Synthesis and Implementation
Example Design
Top-Level Example Design HDL
Support Level HDL
Block Level HDL
Transceiver Files for Zynq 7000 SoC, Virtex 7, Kintex 7, or Artix 7 Devices
Transceiver Wrapper
Zynq 7000 SoC, Virtex 7, Kintex 7, and Artix 7 Device Transceiver Wizard Files
QSGMII Adaptation Module
Test Bench
Test Bench Functionality
Customizing the Test Bench
Changing Frame Data
Changing Frame Error Status
Changing the Core Configuration
Changing the Operational Speed
Verification, Compliance, and Interoperability
Simulation
Hardware Testing
Compliance Testing
Upgrading
Migrating
Device Migration
Migrating to the Vivado Design Suite
Upgrading in the Vivado Design Suite
Shared Logic
Port Changes from v3.2 to v3.3
Port Changes from v3.0 to v3.1
Port Changes from v2.0 to v3.0
Ports Added
Ports Moved
Ports Removed
Implementing External GMII/MII
External GMII Transmitter Logic
External MII Transmitter Logic
External GMII/MII Receiver Logic
Debugging
Finding Help with AMD Adaptive Computing Solutions
Documentation
Solution Centers
Answer Records
Technical Support
Debug Tools
Vivado Design Suite Debug Feature
Vivado Design Suite Debug Feature
Reference Boards
Simulation Debug
Hardware Debug
General Checks
Problems with the MDIO
Problems with Data Reception or Transmission
Problems with Auto-Negotiation
Problems in Obtaining a Link (Auto-Negotiation Disabled)
Problems with a High Bit Error Rate
Symptoms
Debugging
Additional Resources and Legal Notices
Finding Additional Documentation
Documentation Portal
Documentation Navigator
Design Hubs
Support Resources
References
Specifications
Revision History
Please Read: Important Legal Notices

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