Latency
These measurements are for the core only; they do not include the latency through the AMD Versal™ Adaptive SoC families, AMD UltraScale+™ families, AMD UltraScale™ architecture, AMD Zynq™ 7000 SoC, AMD Virtex™ 7, AMD Kintex™ 7, or AMD Artix™ 7 device transceiver, or the Transmitter Elastic Buffer added in the QSGMII core.
Transmit Path Latency
As measured from a data octet input into
gmii_txd[7:0] of the transmitter side GMII of SGMII on port 0 (until that
data appears on txdata[7:0] on the serial transceiver interface), the
latency through the core in the transmit direction is five clock periods of
userclk2.
Receive Path Latency
Receive Path Latency is variable because of an elastic
buffer on each lane for clock compensation; therefore, the latency is measured from the
output of the elastic buffer until the octet appears on the receiver side GMII. As measured
from a data octet output from the elastic buffer until that data appears on
gmii_rxd[7:0] of the receiver side GMII of port 0, the latency through
the core in the receive direction is six clock periods of userclk2.
Throughput
QSGMII Interface operates at a full line rate of 5 Gb/s.