PCS Receive Engine and Synchronization - 3.5 English

Quad Serial Gigabit Media Independent LogiCORE Product Guide (PG029)

Document ID
PG029
Release Date
2023-11-02
Version
3.5 English

The synchronization process implements the state diagram of IEEE 802.3-2008 (Figure 36-9). The PCS receive engine converts the sequence of ordered sets to GMII data octets by implementing the state diagrams of IEEE 802.3-2008 Specification [Ref 2] (Figures 36-7a and 36-7b). This module can be programmed to optionally consider disparity. Disparity checking is disabled by default.