Overview - Overview - 4.0 English - PG029

Quad Serial Gigabit Media Independent LogiCORE IP Product Guide (PG029)

Document_ID: PG029
Release_Date: 2025-12-09
Version: 4.0 English

Introduction
Features
IP Facts
Overview
Navigating Content by Design Process
Core Overview
System Overview
Feature Summary
Applications
Licensing and Ordering
Product Specification
Standards
Performance
Resource Utilization
Port Descriptions
Transceiver Control and Status Ports
Register Space
MDIO Management System
MDIO Bus System
MDIO Transactions
Write Transaction
Read Transaction
MDIO Addressing
Physical Address (PHYAD)
Register Address (REGAD)
Connecting the MDIO to an Internally Integrated STA
Connecting the MDIO to an External STA
Management Registers
QSGMII Using Optional Auto-Negotiation
Register 0: SGMII Control Register
MDIO REGISTER 0: SGMII CONTROL CHANNELS 1-3
Register 1: SGMII Status Register
Registers 2 and 3 (PHY IDENTIFIER)
Register 4: SGMII Auto-Negotiation Advertisement
Register 5: SGMII Auto-Negotiation Link Partner Ability
Register 6: SGMII Auto-Negotiation Expansion
Register 7: SGMII Auto-Negotiation Next Page Transmit
Register 8: SGMII Next Page Receive
Register 15: SGMII Extended Status
Register 16: SGMII Auto-Negotiation Interrupt Control
Register 18: SGMII Generic Control
QSGMII Without Optional Auto-Negotiation
Register 0: SGMII Control Register
Management Registers Channels/Modules 1-3
Register 1: SGMII Status Register
Link Status
Registers 2 and 3 (PHY IDENTIFIER)
Register 15: SGMII Extended Status
Register 18: SGMII Generic Control (Register 18)
Designing with the Core
Design Guidelines
Shared Logic
Clocking
Resets
Using the Client Side GMII/MII Datapath
Using the Encrypted Core Level Client-Side GMII/MII
GMII Transmission
GMII Reception
MII Transmission
MII Reception
Additional Client-Side QSGMII Adaptation Logic
QSGMII Adaptation Module Top-Level
SGMII Adaptation Module Top-Level
Transmitter Rate Adaptation Module
Receiver Rate Adaptation Module
Clock Generation Module
Using the Transceiver
Transceiver Logic
Clock Sharing Across Multiple Cores with Transceivers
Design Flow Steps
Customizing and Generating the Core
Constraining the Core
Device, Package, and Speed Grade Selections
I/O Location Constraints
Placement Constraints
Transceiver Placement
Versal GTY Transceivers
Virtex 7 FPGA GTH Transceivers
Virtex 7 FPGA GTX Transceivers
Zynq 7000 SoC and Kintex 7 FPGA GTX Transceivers
Artix 7 FPGA GTP Transceivers
Constraints When Using External GMII/MII
Zynq 7000 SoC, Virtex 7, Kintex 7, and Artix 7 Devices
Simulation
Synthesis and Implementation
Example Design
Top-Level Example Design HDL
Support Level HDL
Block Level HDL
Transceiver Files for Zynq 7000 SoC, Virtex 7, Kintex 7, or Artix 7 Devices
QSGMII Adaptation Module
Test Bench
Test Bench Functionality
Customizing the Test Bench
Verification, Compliance, and Interoperability
Simulation
Hardware Testing
Compliance Testing
Upgrading
Migrating
Upgrading in the Vivado Design Suite
Implementing External GMII/MII
External GMII Transmitter Logic
External MII Transmitter Logic
External GMII/MII Receiver Logic
Debugging
Finding Help with AMD Adaptive Computing Solutions
Debug Tools
Simulation Debug
Hardware Debug
Additional Resources and Legal Notices
Finding Additional Documentation
Support Resources
References
Revision History
Please Read: Important Legal Notices

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