Migrating - 4.0 English - PG029

Device Migration

If you are migrating from a 7 series device to an AMD UltraScale+™ families or AMD UltraScale™ architecture, the prefix of the optional transceiver debug ports for single-lane cores is changed from gt0 or gt1 to gt, and the postfix _in and _out are dropped.

For multi-lane cores, the prefixes of the optional transceiver debug ports gt(n) are aggregated into a single port. For example, gt0_gtrxreset and gt1_gtrxreset become gt_gtrxreset [1:0].

This is true for all ports except DRP buses, which follow the convention gt(n)_drpxyz.

It is important to update your design to use the new transceiver debug port names. For more information about migration to AMD UltraScale™ devices, see the UltraScale Architecture Migration: Methodology Guide (UG1026).

Migrating to the Vivado Design Suite

For information on migrating to the AMD Vivado™ Design Suite, see the ISE to Vivado Design Suite Migration Guide (UG911).