All ports in the encrypted hierarchy of the core are internal connections in FPGA logic. Un-encrypted HDL in the core and example design (delivered with the core) connect the core, where appropriate, to a device-specific transceiver, and/or add IBUFs, OBUFs, and IOB flip-flops to the external signals of the GMII/MII. IOBs are added to the remaining unconnected ports to take the example design through the Xilinx implementation software. All the ports described here indicate the pins at the in the encrypted hierarchy of the core level. The block level design instantiates the core and transceiver.
All clock management logic is placed in this example design, allowing you more flexibility in implementation (such as designs using multiple cores). This example design is provided in both VHDL and Verilog.
This Figure shows the pinout for the QSGMII core using a device-specific transceiver with the optional MDIO Management and optional Auto-Negotiation.
The port name for multiple instances of an interface is generalized as “CHx.” “CHx” takes the value “CH0,” “CH1,” “CH2,” and “CH3.”
|
This Figure shows the pinout for the QSGMII core using a device-specific transceiver with only the optional MDIO Management. The port name for multiple instances of an interface is generalized as “CHx.” “CHx” takes the value “CH0,” “CH1,” “CH2,” and “CH3.”
|
This Figure shows the pinout for the QSGMII core using a device-specific transceiver with only the optional Auto-Negotiation.
The port name for multiple instances of an interface is generalized as “CHx.” “CHx” takes the value “CH0,” “CH1,” “CH2,” and “CH3.”
|
This Figure shows the pinout for the QSGMII core using a device-specific transceiver without optional MDIO or Auto-Negotiation.
The port name for multiple instances of an interface is generalized as “CHx.” “CHx” takes the value “CH0,” “CH1,” “CH2,” and “CH3.”
