Implement the QSGMII Core in Your Application - 3.5 English

Quad Serial Gigabit Media Independent LogiCORE Product Guide (PG029)

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3.5 English

Before implementing your application, examine the example design delivered with the core for information about the following:

Instantiating the core from HDL

Connecting the physical-side interface of the core

Deriving the clock management logic

It is expected that the block-level module from the example design is instantiated directly into customer designs rather than the core netlist itself. The block level contains the core and a completed physical interface.