• Ensure that all the timing constraints for the core were met during Place and Route.
• Ensure that all clock sources are clean. If using DCMs in the design, ensure that all DCMs have obtained lock by monitoring the locked port.
• Ensure that all the timing constraints for the core were met during Place and Route.
• Ensure that all clock sources are clean. If using DCMs in the design, ensure that all DCMs have obtained lock by monitoring the locked port.