The following constraints target the flip-flops that are inferred in the top-level HDL file for the example design. These constraints are defined for receive signals; the transmit GMII/MII interface passes through IDELAY modules to adjust for latency. See GMII Input Setup/Hold Timing . Constraints are set to ensure that these are placed in IOBs.
#***********************************************************
# GMII Receiver Constraints: place flip-flops in IOB *
#***********************************************************
set_property IOB TRUE [get_cells gmii_rxd_ch0_obuf_reg*]
set_property IOB TRUE [get_cells gmii_rx_dv_ch0_obuf_reg*]
set_property IOB TRUE [get_cells gmii_rx_er_ch0_obuf_reg*]
set_property IOB TRUE [get_cells gmii_rxd_ch1_obuf_reg*]
set_property IOB TRUE [get_cells gmii_rx_dv_ch1_obuf_reg*]
set_property IOB TRUE [get_cells gmii_rx_er_ch1_obuf_reg*]
set_property IOB TRUE [get_cells gmii_rxd_ch2_obuf_reg*]
set_property IOB TRUE [get_cells gmii_rx_dv_ch2_obuf_reg*]
set_property IOB TRUE [get_cells gmii_rx_er_ch2_obuf_reg*]
set_property IOB TRUE [get_cells gmii_rxd_ch3_obuf_reg*]
set_property IOB TRUE [get_cells gmii_rx_dv_ch3_obuf_reg*]
set_property IOB TRUE [get_cells gmii_rx_er_ch3_obuf_reg*]
Virtex 7 devices support GMII at 3.3V or lower only in certain parts and packages. See the Virtex 7 device documentation. GMII/MII by default is supported at 3.3V and the XDC contains the following syntax. Use this syntax together with the device I/O Banking rules.
#***********************************************************
# GMII IOSTANDARD Constraints: please select an I/O *
# Standard (LVTTL is suggested). *
#***********************************************************
set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd_ch0[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports gmii_tx_en_ch0]
set_property IOSTANDARD LVCMOS33 [get_ports gmii_tx_er_ch0]
set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd_ch0[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports gmii_rx_dv_ch0]
set_property IOSTANDARD LVCMOS33 [get_ports gmii_rx_er_ch0]
set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd_ch1[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports gmii_tx_en_ch1]
set_property IOSTANDARD LVCMOS33 [get_ports gmii_tx_er_ch1]
set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd_ch1[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports gmii_rx_dv_ch1]
set_property IOSTANDARD LVCMOS33 [get_ports gmii_rx_er_ch1]
set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd_ch2[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports gmii_tx_en_ch2]
set_property IOSTANDARD LVCMOS33 [get_ports gmii_tx_er_ch2]
set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd_ch2[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd_ch0[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports gmii_rx_dv_ch0]
set_property IOSTANDARD LVCMOS33 [get_ports gmii_rx_er_ch0]
set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd_ch1[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports gmii_tx_en_ch1]
set_property IOSTANDARD LVCMOS33 [get_ports gmii_tx_er_ch1]
set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd_ch1[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports gmii_rx_dv_ch1]
set_property IOSTANDARD LVCMOS33 [get_ports gmii_rx_er_ch1]
set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd_ch2[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports gmii_tx_en_ch2]
set_property IOSTANDARD LVCMOS33 [get_ports gmii_tx_er_ch2]
set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd_ch2[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports gmii_rx_dv_ch2]
set_property IOSTANDARD LVCMOS33 [get_ports gmii_rx_er_ch2]
set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd_ch3[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports gmii_tx_en_ch3]
set_property IOSTANDARD LVCMOS33 [get_ports gmii_tx_er_ch3]
set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd_ch3[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports gmii_rx_dv_ch3]
set_property IOSTANDARD LVCMOS33 [get_ports gmii_rx_er_ch3]
set_property IOSTANDARD LVCMOS33 [get_ports gtx_clk_ch0]
set_property IOSTANDARD LVCMOS33 [get_ports gtx_clk_ch1]
set_property IOSTANDARD LVCMOS33 [get_ports gtx_clk_ch2]
set_property IOSTANDARD LVCMOS33 [get_ports gtx_clk_ch3]