This interface is enabled in the MAC mode or GMII configuration of PHY mode. In the MAC mode this interface is expected to be connected to the GMII interface of Tri-Mode Ethernet MAC core (TEMAC). In the GMII configuration of PHY mode, this interface is brought out onto the pads.
Table 2-7:
GMII Interface Signals Pinout
|
Signal
|
Direction
|
Description
|
|
gmii_txd_chx[7:0]
(1)
|
Input
|
GMII Transmit data
|
|
gmii_txd_en_chx
(1)
|
Input
|
GMII Transmit data enable
|
|
gmii_tx_er_chx
(1)
|
Input
|
GMII Transmit error
|
|
gmii_rxd_chx[7:0]
(2)
|
Output
|
GMII Receive data
|
|
gmii_rxd_dv_chx
(2)
|
Output
|
GMII Receive data valid
|
|
gmii_rx_er_chx
(2)
|
Output
|
GMII Receive error
|
|
gtx_clk_chx
|
Input
|
GMII TX clock. This is valid only in GMII configuration in PHY mode
|
|
gmii_rx_clk_chx
|
Output
|
GMII RX clock. This is valid only in GMII configuration in PHY mode
|
|
sgmii_clk_en_chx
|
Output
|
Clock enables. This valid only in MAC mode.
|
|
sgmii_clk_en_rx_chx
|
Output
|
Clock enables. This valid only in MAC mode and when RX path is on rxuserclk2.
|
|
Notes:
1.
In MAC mode these signals are synchronous to 125 MHz reference clock of the core, that is,
userclk2
. In GMII configuration of PHY mode these signals are synchronous to
gtx_clk_chx
and these signals are synchronized to
userclk2
domain using Transmit Elastic Buffer present in the block
2.
These signals are synchronous to 125 MHz reference clock of the core. This is
userclk2
.
|
Table 2-8:
MII Interface Signals Pinout
|
Signal
|
Direction
|
Description
|
|
mii_txd_chx[7:0]
(1)
|
Input
|
MII Transmit data
|
|
mii_tx_en_chx
(1)
|
Input
|
MII Transmit data enable
|
|
mii_tx_er_chx
(1)
|
Input
|
MII Transmit error
|
|
mii_rxd_chx[7:0]
(2)
|
Output
|
MII Receive data
|
|
mii_rx_dv_chx
(2)
|
Output
|
MII Receive data valid
|
|
mii_rx_er_chx
(2)
|
Output
|
MII Receive data error
|
|
mii_tx_clk_chx
|
Output
|
MII TX clock. This is valid only in MII configuration in MII mode. The clock can be 2.5/25 MHz based on 10/100 Mbps mode of operation
|
|
mii_rx_clk_chx
|
Output
|
MII RX clock. This is valid only in MII configuration in MII mode. The clock can be 2.5/25 MHz based on 10/100 Mbps mode of operation
|
|
Notes:
1.
These signals should be driven on
mii_tx_clk_chx
.
2.
These signals are synchronous to
mii_rx_clk_chx
.
|