GMII Input Setup/Hold Timing - 3.5 English - PG029

This Figure and Table: Input GMII Timings illustrate the setup and hold time window for the input GMII signals. These are the worst-case data valid window presented to the FPGA pins.

Observe that there is, in total, a 2 ns data valid window of guaranteed data that is presented across the GMII input bus. This must be correctly sampled by the FPGA devices.