- Integrated transceiver interface using AMD Versal™
Adaptive SoC GTY/GTYP transceiver
- Integrated transceiver interface using AMD UltraScale+™
families, AMD UltraScale™
architecture, and AMD Virtex™ 7 FPGA GTH transceiver
- Integrated transceiver interface using an AMD Zynq™
7000 SoC, AMD
Virtex 7, and AMD
Kintex 7 device GTX
transceiver
- Integrated transceiver interface using AMD
Artix™
7 FPGA GTP transceiver
- Implements SGMII Adaptation to support 10/100/1000 operation
for each port
- Transmitters of all ports transmit only /I1/ Idle ordered
set
- Lane alignment based on K28.1 character detection
- Implements QSGMII K28.5 swapper on Port 0 transmit path
- Implements QSGMII K28.1 swapper on Port 0 receive path
- Implements receive link synchronization state machine
- Programmable Decoder running disparity checking for each
port
- Supports full duplex mode only