• Integrated transceiver interface using AMD Versal ™ Adaptive SoC GTY/GTYP transceiver
• Integrated transceiver interface using AMD UltraScale+ ™ families, AMD UltraScale™ architecture, and Virtex 7 FPGA GTH transceiver
• Integrated transceiver interface using an AMD Zynq ™ 7000 SoC, AMD Virtex ™ 7, and AMD Kintex ™ 7 device GTX transceiver
• Integrated transceiver interface using AMD Artix ™ 7 FPGA GTP transceiver
• Implements SGMII Adaptation to support 10/100/1000 operation for each port
• Transmitters of all ports transmit only /I1/ Idle ordered set
• Lane alignment based on K28.1 character detection
• Implements QSGMII K28.5 swapper on Port 0 transmit path
• Implements QSGMII K28.1 swapper on Port 0 receive path
• Implements receive link synchronization state machine
• Programmable Decoder running disparity checking for each port
• Supports full duplex mode only
LogiCORE IP Facts Table |
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Core Specifics |
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Supported Device Family (1) |
AMD Versal Adaptive SoC, AMD UltraScale+, AMD UltraScale, Zynq 7000,
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Supported User Interfaces |
GMII/MII |
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Resources |
See Performance and Resource Utilization web page. |
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Provided with Core |
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Design Files |
Encrypted RTL |
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Example Design |
VHDL and Verilog |
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Test Bench |
Demonstration Test Bench in VHDL and Verilog |
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Constraints File |
Xilinx Design Constraints (XDC) |
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Simulation Model |
Verilog and VHDL |
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Supported
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N/A
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Tested Design Flows (2) |
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Design Entry |
AMD Vivado ™ Design Suite |
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Simulation |
For supported simulators, see the
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Synthesis |
Vivado Synthesis |
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Simulation Model |
Verilog and VHDL |
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Support |
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Release Notes and Known Issues |
Master Answer Record: 54668 |
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All Vivado IP Change Logs |
Master Vivado IP Change Logs: 72775 |
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Notes: 1. For a complete list of supported devices, see the Vivado IP catalog .
2.
For the supported versions of the tools, see the
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