- The core has two modes of operation.
- Media Access Controller (MAC) mode to connect to a customized MAC or AMD Tri-Mode Ethernet MAC AMD LogiCORE™ IP operating in Internal Mode. See QSGMII MAC.
- Physical-side interface (PHY) mode to connect to an external PHY through Gigabit Media Independent Interface/Media Independent Interface (GMII/MII). See QSGMII PHY.
- Each port configured and monitored through independent a serial MDIO interface, which can optionally be omitted from the core. An additional configuration vector interface is provided that can be used to program registers 0 and 4 over and above the MDIO interface.
- Supports Auto-Negotiation according to IEEE 802.3-2008 Clause 37 on each port for information exchange with a link partner, which can optionally be omitted from the core.
- Integrated transceiver interface using a Zynq 7000 SoC, Virtex 7, and Kintex 7 device GTX transceiver.
- Integrated transceiver interface using an UltraScale+ families, UltraScale architecture, and Virtex 7 FPGA GTH transceiver.
- Integrated transceiver interface using an AMD Versal™ Adaptive SoC GTY transceiver.
- Integrated transceiver interface using Artix 7 FPGA GTP transceiver.
- Implements SGMII Adaptation to support 10/100/1000 operation for each port. Each port can be programmed to operate at a speed independent of other ports.
- Transmitters of all ports transmit only /I1/ Idle ordered set.
- Lane alignment based on K28.1 character detection.
- Implements QSGMII K28.5 swapper on Port 0 transmit path.
- Implements QSGMII K28.1 swapper on Port 0 receive path.
- Implements receive link synchronization state machine.
- Programmable Decoder running disparity checking for each port.
- Supports maximum frame size of 2.8 KB for 10 Mb/s, 28 KB for 100 Mb/s and 280 KB for 1 Gb/s per single lane.
Note: By default, the QSGMII core does not support half-duplex
mode. To request this functionality, contact your local AMD support
representative.