When implementing an external MII, the MII transmitter signals are synchronous to the core internal 125 MHz clock ( userclk2 ).
IODELAY elements on the data are used to delay the data by fixed duration depending on the application. The delayed data is then sampled on core internal clock ( userclk2 ), as illustrated in This Figure .
The IODELAY elements can be adjusted to fine-tune the setup and hold times at the MII IOB input flip-flops. The delay is applied to the IODELAY element using constraints in the Example Design level XDC; these can be edited if desired.
