The figure below illustrates an external GMII receiver created in a Virtex 7 device. The signal names and logic shown in the figure exactly match those delivered in the QSGMII block when the GMII is selected. If other families are selected, equivalent primitives and logic specific to that family are automatically used in the QSGMII block.
The figure also shows that the output receiver signals are registered in device IOBs before driving them to the device pads. All receiver logic is synchronous to a single clock domain.
Figure 1. External GMII/MII Receiver Logic
