External GMII Transmitter Logic - 3.5 English

Quad Serial Gigabit Media Independent LogiCORE Product Guide (PG029)

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3.5 English

When implementing an external GMII, the GMII transmitter signals are synchronous to their own clock domain. The core must be used with a Transmitter Elastic Buffer to transfer these GMII transmitter signals onto the cores internal 125 MHz reference clock ( userclk2 ). A Transmitter Elastic Buffer is embedded in the block level of the core.

Using a combination of IODELAY elements on the data and using BUFIO and BUFR regional clock routing for the gtx_clk_chx input clock, are illustrated in This Figure .

In this implementation, a BUFIO is used to provide the lowest form of clock routing delay from the input clock to the input GMII TX signal sampling at the device IOBs. Note, however, that this creates placement constraints; a BUFIO capable clock input pin must be selected, and all other input GMII TX signals must be placed in the respective BUFIO region. The device FPGA user guides should be consulted.

The clock is then placed onto regional clock routing using the BUFR component and the input GMII TX data immediately resampled as illustrated.

The IODELAY elements can be adjusted to fine-tune the setup and hold times at the GMII IOB input flip-flops. The delay is applied to the IODELAY element using constraints in the XDC; these can be edited if desired.

Figure C-1: External GMII Transmitter Logic

X-Ref Target - Figure C-1