Example Design - 4.0 English - PG029

Quad Serial Gigabit Media Independent LogiCORE IP Product Guide (PG029)
Document ID
PG029
Release Date
2025-12-09
Version
4.0 English

This chapter provides detailed information about the deliverables provided by the AMD Vivado™ Design Suite for the QSGMII core.

The following figure illustrates an example design for top-level HDL for the QSGMII using a device-specific transceiver (AMD UltraScale+™ families, AMD UltraScale™ architecture, AMD Zynq™ 7000 SoC, AMD Virtex™ 7, AMD Kintex 7, or AMD Artix™ 7 devices).

Figure 1. Example Design HDL for QSGMII Page-1 Sheet.1 component_name_example_design component_name_example_design Sheet.2 component_name_block component_name_block Sheet.3 Sheet.4 Transceiver Transceiver Sheet.5 Device Specific Transceiver Device Specific Transceiver Sheet.6 Sheet.7 Sheet.8 Quad Serial GMII Quad Serial GMII Sheet.9 QSGMII Core QSGMII Core Sheet.10 Sheet.11 Sheet.12 QSGMII Adaptation Module QSGMII Adaptation Module Sheet.13 Sheet.14 Sheet.15 IOBs In IOBs In Sheet.16 IOBs Out IOBs Out Sheet.17 GMII CH0 GMII CH0 Sheet.18 Sheet.19 Sheet.20 Sheet.21 IOBs In IOBs In Sheet.22 IOBs Out IOBs Out Sheet.23 GMII CH1 GMII CH1 Sheet.24 Sheet.25 Sheet.26 Sheet.27 IOBs In IOBs In Sheet.28 IOBs Out IOBs Out Sheet.29 GMII CH2 GMII CH2 Sheet.30 Sheet.31 Sheet.32 Sheet.33 IOBs In IOBs In Sheet.34 IOBs Out IOBs Out Sheet.35 GMII CH3 GMII CH3 Sheet.36 Sheet.37 Sheet.38 Sheet.39 Sheet.40 Sheet.41 Sheet.42 Sheet.43 Sheet.44 Sheet.45 Sheet.46 Sheet.47 Sheet.48 Sheet.49 Sheet.50 Sheet.51 Sheet.52 GMII Style IF GMII Style IF Sheet.53 GMII Style IF GMII Style IF Sheet.54 GMII Style IF GMII Style IF Sheet.55 GMII Style IF GMII Style IF Sheet.56 Clock Management Logic Clock Management Logic Sheet.57 X13234 X13234-030224

As illustrated, the example is split between two hierarchical layers. The block level is designed so that it can be instantiated directly into customer designs and performs the following functions:

  • Instantiates the core from HDL
  • Connects the physical-side interface of the core to a device-specific transceiver
  • Implements an external GMII-style interface
  • Connects the client side GMII of the core to an QSGMII Adaptation Module, which provides the functionality to operate at speeds of 1 Gb/s, 100 Mb/s and 10 Mb/s

The top-level of the example design creates a specific example which can be simulated, synthesized, and implemented. The top-level of the example design performs the following functions:

  • Instantiates the block level from HDL in case shared logic in the core is selected, otherwise support level.
  • Derives the clock management logic for device-specific transceiver and the core.

The Versal Adaptive SoC example design supports two primary GT Wizard configurations. The following figure illustrates the use of the Legacy GT Wizard within an IP-integrated block design flow.

Figure 2. QSGMII IP with Legacy GT Wizard for Versal Devices

The following figure shows the new GT Wizard Subsystem implemented in an RTL-based hierarchical structure that exposes all sub-cores. You can enable either configuration by selecting the Use Legacy GT Wizard in Example Design option in the IP GUI.

Figure 3. QSGMII IP with GT Wizard Subsystem for Versal Devices

The next few pages in this section describe each of the example design blocks (and associated HDL files) in detail. The example design can be opened in a separate project by generating the Examples output product, right-click the core instance, and select Open IP Example Design.