This chapter provides detailed information about the deliverables provided by the AMD Vivado ™ Design Suite for the QSGMII core.
This Figure illustrates an example design for top-level HDL for the QSGMII using a device-specific transceiver (UltraScale+™ families, UltraScale™ architecture, AMD Zynq ™ 7000 SoC, AMD Virtex ™ 7, AMD Kintex ™ 7, or AMD Artix ™ 7 devices).
As illustrated, the example is split between two hierarchical layers. The block level is designed so that it can be instantiated directly into customer designs and performs the following functions:
• Instantiates the core from HDL
• Connects the physical-side interface of the core to a device-specific transceiver
• Implements an external GMII-style interface
• Connects the client side GMII of the core to an QSGMII Adaptation Module, which provides the functionality to operate at speeds of 1 Gbps, 100 Mbps and 10 Mbps
The top-level of the example design creates a specific example which can be simulated, synthesized, and implemented. The top-level of the example design performs the following functions:
• Instantiates the block level from HDL in case shared logic in the core is selected, otherwise support level.
• Derives the clock management logic for device-specific transceiver and the core.
The next few pages in this section describe each of the example design blocks (and associated HDL files) in detail. The example design can be opened in a separate project by generating the Examples output product, right-click the core instance, and select Open IP Example Design.. .