An HDL example design built around the core is provided through the Vivado design tools that allows for a demonstration of core functionality using either a simulation package or in hardware if placed on a suitable board.
Example designs are provided depending upon the core customization options that are selected. See Example Design .
Before implementing the core in your application, examine the example design provided with the core to identify the steps that can be performed:
1. Edit the HDL top-level of the example design file to change the clocking scheme, add or remove IOBs as required
2. Synthesize the entire design.
3.
Implement the entire design.
After implementation is complete, you can also create a bitstream that can be downloaded to a Xilinx
®
device.
4. Download the bitstream to a target device.