Understand the Core Netlist Features and Interfaces
This chapter assumes a working knowledge of the IEEE 802.3-2008 Specification, in particular the Gigabit Ethernet 1000BASE-X sections: clauses 34 through to 37 and SGMII and QSGMII Cisco Specifications.
Customize and Generate the Core
Generate the core with your desired options using the AMD Vivado™ IP catalog as described in Customizing and Generating the Core.
Examine the Example Design
An HDL example design built around the core is provided through the AMD Vivado™ design tools that allows for a demonstration of core functionality using either a simulation package or in hardware if placed on a suitable board.
Example designs are provided depending upon the core customization options that are selected. See Example Design.
Before implementing the core in your application, examine the example design provided with the core to identify the steps that can be performed:
- Edit the HDL top-level of the example design file to change the clocking scheme, add or remove IOBs as required
- Synthesize the entire design.
- Implement the entire design. After implementation is complete, you can also create a bitstream that can be downloaded to an AMD device.
- Download the bitstream to a target device.
Implement the QSGMII Core in Your Application
Before implementing your application, examine the example design delivered with the core for information about the following:
- Instantiating the core from HDL
- Connecting the physical-side interface of the core
- Deriving the clock management logic
It is expected that the block-level module from the example design is instantiated directly into customer designs rather than the core netlist itself. The block level contains the core and a completed physical interface.
Write an HDL Application
After reviewing the example design delivered with the core, write an HDL application that uses single or multiple instances of the block level module for the QSGMII core.
Synthesize your Design and Create a Bitstream
Synthesize your entire design using the desired synthesis tool. Carefully constrain the design correctly; the constraints provided with the core should be used as the basis for your own. See the constraint chapters in the Vivado Design Suite as appropriate.
Simulate and Download your Design
After creating a bitstream that can be downloaded to an AMD device, simulate the entire design and download it to the desired device.
Know the Degree of Difficulty
An QSGMII core is challenging to implement in any technology and as such, all QSGMII core applications require careful attention to system performance requirements. Pipelining, logic mapping, placement constraints, and logic duplication are all methods that help boost system performance.
Keep it Registered
To simplify timing and to increase system performance in an FPGA design, keep all inputs and outputs registered between the user application and the core. All inputs and outputs from the user application should come from, or connect to, a flip-flop. While registering signals might not be possible for all paths, it simplifies timing analysis and makes it easier for the AMD tools to place and route the design.
Recognize Timing Critical Signals
The constraints provided with the example design for the core identifies the critical signals and the timing constraints that should be applied. See Constraining the Core.
Make Only Allowed Modifications
The QSGMII core should not be modified. Modifications can have adverse effects on system timing and protocol compliance. Supported user configurations of the QSGMII core can only be made by selecting the options from within the Vivado design tools when the core is generated. See the Vivado IP catalog: Customizing and Generating the Core.